ISL6610 Datasheet, PDF (7/11 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6610, ISL6610A
the bootstrap capacitor when exposed to excessively large
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
that use D²-PAK and D-PAK MOSFETs or excessive layout
parasitic inductance. The following equation helps select a
proper bootstrap capacitor size:
C _{B O O T _CAP}
≥
----------^Q-----^G----^A----^T---^E-----------
Δ V_{B O O T _CAP}
(EQ. 1)
Q_GATE=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_---
V_GS1
•
N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two HAT2168 FETs are chosen as
the upper MOSFETs. The gate charge, Q_G, from the data
sheet is 12nC at 5V (V_GS) gate-source voltage. Then the
Q_GATE is calculated to be 26.4nC at 5.5V PVCC level. We
will assume a 100mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.264μF is required. The next larger standard value
capacitance is 0.33µF. A good quality ceramic capacitor is
recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_BOOT (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F_SW), the output drive impedance, the
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO14 package is approximately 1W at room
temperature, while the power dissipation capacity in the
QFN packages, with an exposed heat escape pad, is around
2W. See Layout Considerations paragraph for thermal
transfer improvement suggestions. When designing the
driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
P_{Qg_TOT} = 2 • (P_{Qg_Q1} + P_{Qg_Q2}) + I_Q • VCC
P _{Q g _Q1}
=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_-----²_-
V_GS1
•
F_SW
•
N_Q
1
P _{Q g _Q2}
=
Q_{-----G-----2----}•_-----P_----V_----C_-----C_-----²_-
V_GS2
•
F_S
W
•
N_Q
2
(EQ. 2)
I_DR
=
2
•
⎛
⎜
⎝
-^Q----^G-----¹----^•-----^N----^Q-----¹-
V_GS1
+
Q_{-----G---V--2--G--}•_--S---N_{-2---Q-----2-⎠⎟⎞}
• F_SW + I_Q
(EQ. 3)
where the gate charge (Q_G1 and Q_G2) is defined at a
particular gate to source voltage (V_GS1and V_GS2) in the
corresponding MOSFET datasheet; I_Q is the driver’s total
quiescent current with no load at both drive outputs and can
be negligible; N_Q1 and N_Q2 are number of upper and lower
MOSFETs, respectively. The factor 2 is the number of active
channels. The I_Q V_CC product is the quiescent power of the
driver without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R_G1 and R_G2, should be a short to avoid
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R_GI1 and R_GI2) of
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
P_DR = 2 • (P_{DR_UP} + P_{DR_LOW}) + I_Q • VCC
(EQ. 4)
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
-_R----_L---_O-----₁^R----+-^L---^O-_R----¹-_E----_X----_T---₁- _{⎠⎟⎞}
• ^P-----^Q----^g----^_--^Q-----¹-
2
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
•
P_{-----Q----g----_--Q-----2-}
2
R_EXT2
=
R_G1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
7
FN6395.0
November 22, 2006