ISL6529A Datasheet, PDF (9/15 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

ISL6529A
However, since the value of R1 affects the values of the rest
of the compensation components, it is advisable to keep its
value less than 5kΩ. Depending on the value chosen for R1,
R4 can be calculated based on the following equation:
R4 = ------R-----1-----^×----0----.-8----V--------
V_OUT1 – 0.8V
(EQ. 1)
If the output voltage desired is 0.8V, simply route VOUT1
back to the FB pin through R1, but do not populate R4.
The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 5. The two
resistors used to set the output voltage should not exceed a
parallel equivalent value, referred to as R_FB, of 5kΩ. This
restriction is due to the manner of implementation of the soft-
start function. The following relationship must be met:
R_FB
=
R-----5-----×_{-----R-----6-}
R5 + R6
<
5kΩ
(EQ. 2)
+3.3V_IN
V_OUT2
+
C_OUT2
Q3
DRIVE2
R12 _C4
FB2
R5
R6
ISL6529A
VOUT2
=
0.8
×


1
+
RR-----56--_
FIGURE 5. OUTPUT VOLTAGE SELECTION OF THE LINEAR
To ensure the parallel combination of the feedback resistors
meets this criteria, choose a target value for R_FB of less than
5kΩ and then apply the following equations:
R5
=
V-----_{O----U----T----2-}
V_REF
×
R_FB
(EQ. 3)
R6 = ------R-----5-----^×----V-----^R----^E----^F-------
V_OUT2 – V_REF
(EQ. 4)
where V_OUT2 is the desired linear regulator output voltage
and V_REF is the internal reference voltage, 0.8V. For an
output voltage of 0.8V, simply populate R5 with a value less
than 5kΩ and do not populate R6.
Converter Shutdown
Pulling and holding the FB2 pin above a typical threshold of
1.28V will shutdown both regulators. Upon release of the
FB2 pin, the regulators enter into a soft-start cycle which
brings both outputs back into regulation.
PWM Controller Feedback Compensation
A simplified representation of the voltage-mode control loop
used for output regulation by the converter is shown in
9
Figure 6. The output voltage, V_OUT, is fed back to the
negative input of the error amplifier which is regulated to the
reference voltage level, V_REF. The error amplifier output,
V_E/A, is compared with the triangle wave produced by the
oscillator, V_OSC, to provide a pulse-width modulated (PWM)
signal from the PWM comparator. This signal is then used to
switch the MOSFET and produce a PWM waveform with an
amplitude of V_IN at the PHASE node. The square-wave
PHASE voltage is then smoothed by the output filter, L_OUT
and C_OUT, to produce a DC voltage level.
The modulator transfer function is defined as V_OUT/V_E/A.
The internal PWM comparator and driver circuits equate to a
DC gain block dominated by the supply voltage, V_IN, divided
by the peak-to-peak magnitude of the triangle wave, ∆V_OSC.
The output filter components, L_OUT and C_OUT, shape the
overall modulator small-signal transfer function by
contributing a double pole break frequency at F_LC and a
zero at F_ESR.
OSC
∆V_OSC
PWM
COMP
-
+
Z_FB
DRIVER
V_IN
L_OUT
V_OUT
PHASE _{CO +}
ESR
(PARASITIC)
V_E/A
Z_IN
+ _VREF
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 _R3
R1
COMP
FB
-
+
ISL6529A
0.8V
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
-------------------1--------------------
2π × L_O × C_O
(EQ. 5)
F_ESR= -2---_π-----_×-----E----S--1---R------_×----C-----_O---
(EQ. 6)
The compensation network consists of the error amplifier
and the impedance networks Z_IN and Z_FB. They provide the
link between the modulator transfer function and a
FN9127.1
December 28, 2004