ISL6529A Datasheet, PDF (10/15 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

ISL6529A
controllable closed loop transfer function of V_OUT/V_REF. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f_0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f_0dB and 180
degrees.
Compensation Break Frequency Equations
Poles:
F_P1
=
---------------------------1----------------------------
2
π
×
R₂
×


C-C----11-----+^{×-----CC-----22--}
(EQ. 8)
F_P2 = _2----π-----_×-----R---1--3-----_×----C-----3--
(EQ. 9)
Zeros:
F_Z1
=
-----------------1------------------
2π × R2 × C1
(EQ. 10)
F_Z2
=
---------------------------1---------------------------
2π × (R1 + R3) × C3
(EQ. 11)
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
1. Set the loop gain (R2/R1) to provide a converter
bandwidth of one quarter of the switching frequency.
2. Place the first compensation zero, F_Z1, below the output
filter double pole (~75% F_LC).
3. Position the second compensation zero, F_Z2, at the
output filter double pole, F_LC.
4. Locate the first compensation pole, F_P1, at the output
filter ESR zero, F_ESR.
5. Position the second compensation pole at half the
converter switching frequency, F_SW.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20 log



V----V-O---I--S-N---C---_{}
60
40
COMPENSATION
GAIN
20
0
-20
20
log


-^RR-----²¹--_
MODULATOR
-40
GAIN
F_LC F_ESR
LOOP GAIN
-60
10
100
1K 10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Figure 7 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 7. Using the above
procedure should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Linear Regulator Feedback Compensation
The regulator may be compensated with a series 6.8kΩ
resistor and a 470pF capacitor connected between FB2 and
DRIVE2. This will provide compensation for all loads and
ranges of output capacitor values and a range of capacitor
ESR values from aluminum electrolytic to low-ESR organic
polymer capacitors. This will not insure optimum load
transient response since the regulator system, like an
internally compensated operational amplifier is
overcompensated.
To optimize transient response, when required, the regulator
should be in the actual application circuit with the desired
output capacitors and associated PC board parasitics and
load. The value of C4 would be reduced and the series
resistor, R12 adjusted for optimum rise and fall time, with a
minimum of overshoot.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes the voltage
spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET and
parasitic diode. Any parasitic inductance in the switched
current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout
of the critical components, and short, wide traces minimizes
the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC converter
using the ISL6529A. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
10
FN9127.1
December 28, 2004