ISL6529A Datasheet, PDF (12/15 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

ISL6529A
ripple current and the ripple voltage is also a function of the
ripple current. The ripple voltage and current are
approximated by the following equations:
∆I
=
V-----_I--N-----–_{----V-----O----U----T--}
F_S × L
×
-V----^O----^U----^T--
V_IN
(EQ. 11)
∆V_OUT = ∆I × ESR
(EQ. 12)
Increasing the value of inductance reduces the output ripple
current and voltage ripple. However, increasing the
inductance value will slow the converter response time to a
load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to slew the inductor
current. Given a sufficiently fast control loop design, the
ISL6529A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the final current level. During this interval the
difference between the inductor current and the load current
must be supplied by the output capacitor(s). Minimizing the
response time can minimize the output capacitance
required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
t_RISE
=
-L---^O------^×-----I--^T---^R----^A----^N---
V_IN – V_OUT
(EQ. 13)
t_FALL
=
L----_O------×_{----I--T----R----A----N--}
V_OUT
(EQ. 14)
where I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load.
With a +3.3V input source, the worst case response time can
be either at the application or removal of load and dependent
upon the output voltage setting. Be sure to check both of
these equations at the minimum and maximum output levels
for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
12
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.
Use a mix of input bypass capacitors to control the voltage
overshoot across the switching MOSFETs. Use ceramic
capacitance for the high frequency decoupling and bulk
capacitors to supply the RMS current. Small ceramic
capacitors can be placed very close to the upper MOSFET
to suppress the voltage induced in the parasitic circuit
impedances. Connect them directly to ground with a via
placed very close to the ceramic capacitor footprint.
For a through-hole design, several aluminum electrolytic
capacitors may be needed. For surface mount designs,
tantalum or special polymer capacitors can be used, but
caution must be exercised with regard to the capacitor surge
current rating. These capacitors must be capable of handling
the surge-current at power-up.
TRANSISTOR SELECTION/CONSIDERATIONS
The ISL6529A requires three external transistors. One
N-Channel MOSFET is used as the upper switch in a
standard buck topology PWM converter. Another MOSFET is
used as the lower synchronous switch. The linear controller
drives the gate of an N-Channel MOS transistor used as the
series pass element. The MOSFET transistors should be
selected based upon r_DS(ON) , gate supply requirements,
and thermal management considerations.
Upper MOSFET SWITCH Selection
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses account for a large portion of the power
dissipation of the upper MOSFET. Switching losses also
contribute to the overall MOSFET power loss.
P_Co
n
du
c
t
i
o
nUp
p
er
≅
I
2
o
×
r_DS(
on
)
×
D
(EQ. 15)
P_Sw
itc
h
i
ng
≅
1--
2
I_o
×
V_I
N
×
t_S
W
×
F_S
W
(EQ. 16)
where I_o is the maximum load current, D is the duty cycle of
the converter (defined as V_O/V_IN), t_SW is the switching
interval, and F_SW is the PWM switching frequency.
The lower MOSFET has only conduction loses since it
switches with zero voltage across the device. Conduction
loss is:
P_Co
n
du
c
t
i
o
nL
o
w
er
≅
I
2
o
×
r_DS(
on
)
×
(
1
–
D
)
(EQ. 17)
These equations assume linear voltage-current transitions
and are approximations. The gate-charge losses are
dissipated by the ISL6529A and do not heat the MOSFET.
However, large gate-charge increases the switching interval,
t_SW, which increases the upper MOSFET switching losses.
FN9127.1
December 28, 2004