ISL6525_04 Datasheet, PDF (9/11 Pages) Intersil Corporation – Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller

ISL6525
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the lower MOSFETs body diode. The
gate-charge losses are dissipated by the ISL6525 and don't
heat the MOSFETs. However, large gate-charge increases
the switching interval, t_SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the ISL6525. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V_CC. The boot capacitor, C_BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V_CC
less the boot diode drop (V_D) when the lower MOSFET, Q2
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V_CC. For Q2, a
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
+12V
VCC
ISL6525
-
+
D_BOOT
+-
V_D
+5V OR +12V
BOOT
UGATE
C_BOOT
Q1
PHASE
NOTE:
V_G-S ≈ V_CC - V_D
+5V
PVCC ^{OR +12V}
LGATE
Q2
PGND
D2
NOTE:
V_G-S ≈ PVCC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
power and +12 VDC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET can be used for Q2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
applied to PVCC.
+12V
VCC
+5V OR LESS
ISL6525
-
+
BOOT
Q1
UGATE
PHASE
+5V
OR +12V
PVCC
Q2
LGATE
PGND
NOTE:
V_G-S ≈ V_CC - 5V
D2
NOTE:
V_G-S ≈ PVCC
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT V_CC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency could slightly decrease
as a result. The diode's rated reverse breakdown voltage must
be greater than the maximum input voltage.
ISL6525 DC-DC Converter Application
Circuit
The figure below shows an application circuit of a DC-DC
converter. Detailed information on the circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in application note AN9916.
Figure 10 shows the upper gate drive supplied by a direct
connection to V_CC. This option should only be used in
converter systems where the main input voltage is +5 VDC
or less. The peak upper gate-to-source voltage is
approximately VCC less the input supply. For +5V main
9
FN4998.3
December 27, 2004