ISL6525_04 Datasheet, PDF (6/11 Pages) Intersil Corporation – Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller

ISL6525
2. The minimum I_OCSET from the specification table.
3. Determine I_PEAK for I_PEAK > I_OUT(MAX) + (∆I) ⁄ 2 ,
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R_OCSET to smooth the voltage across R_OCSET in the
presence of switching noise on the input voltage.
Programming PGOOD Delay Time
The PGOOD rising edge delay can be programmed by
connecting a small capacitor C_DELAY between the DELAY pin
and GND. The rising-edge delay is determined by the 10µA
discharging current source I_DISCH, the voltage difference
between VCC and the gate threshold voltage V_TH of the open-
drain FET, and the capacitor value. The delay time t_DELAY can
be calculated with the following equation,
t_DELAY
=
C_{-----D----E----L----A---Y----}(_---V_----C_-----C_{------–----}V_{-----T---H-----})
I_DISCH
V_TH is typically 2V, VCC is 12V, and I_DISCH is 10µA. Thus,
1nF of C_DELAY leads to 1ms of delay time typically.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
V_IN
ISL6525
UGATE
Q1
PHASE
L_O
V_OUT
LGATE
PGND
Q2 D2
C_IN
C_O
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
Please note that the capacitors C_IN and C_O each represent
numerous physical capacitors. Locate the ISL6525 within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the ISL6525
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C_ss
close to the SS pin because the internal current source is
only 10µA. Provide local V_CC decoupling between VCC and
GND pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins.
BOOT
D1
C_BOOT
ISL6525 ^PHASE
SS
+12V
C_SS
GND
VCC
C_VCC
+V_IN
Q1 _LO
V_OUT
Q2 ^CO
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
OSC
V_IN
DRIVER
PWM
COMPARATOR
L_O
∆V_OSC
-
+
DRIVER
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
PHASE
C_O
ESR
(PARASITIC)
V_OUT
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
ISL6525
-
FB
+
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
6
FN4998.3
December 27, 2004