ISL6523A Datasheet, PDF (9/16 Pages) Intersil Corporation – VRM8.5 Dual PWM and Dual Linear Power System Controller

ISL6523A
OVERCURRENT TRIP:
VDS > VSET
iD × rDS_(ON) > IOCSET × ROCSET
OCSET
V_IN = +5V
R_OCSET
OVER-
CURRENT
OC
+
-
I_OCSET
200µA
DRIVE
V_SET +
VCC
UGATE
i_D
+
V_DS
PHASE
PWM
GATE
CONTROL
VPHASE = VIN – VDS
VOCSET = VIN – VSET
FIGURE 8. OVERCURRENT DETECTION
OUT1 Voltage Program
The output voltage of the PWM1 converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5kΩ resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the overvoltage
protection. The output voltage program is Intel VRM8.5
compatible.
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM
VID3
PIN NAME
VID2
VID1
VID0
VID25
NOMINAL
DACOUT
VOLTAGE
0
1
0
0
0
1.050
0
1
0
0
0
1.050
0
1
0
0
1
1.075
0
0
1
1
0
1.100
0
0
1
1
1
1.125
0
0
1
0
0
1.150
0
0
1
0
1
1.175
0
0
0
1
0
1.200
0
0
0
1
1
1.225
0
0
0
0
0
1.250
0
0
0
0
1
1.275
1
1
1
1
0
1.300
1
1
1
1
1
1.325
1
1
1
0
0
1.350
1
1
1
0
1
1.375
1
1
0
1
0
1.400
1
1
0
1
1
1.425
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM (Continued)
VID3
PIN NAME
VID2
VID1
VID0
VID25
NOMINAL
DACOUT
VOLTAGE
1
1
0
0
0
1.450
1
1
0
0
1
1.475
1
0
1
1
0
1.500
1
0
1
1
1
1.525
1
0
1
0
0
1.550
1
0
1
0
1
1.575
1
0
0
1
0
1.600
1
0
0
1
1
1.625
1
0
0
0
0
1.650
1
0
0
0
1
1.675
0
1
1
1
0
1.700
0
1
1
1
1
1.725
0
1
1
0
0
1.750
0
1
1
0
1
1.775
0
1
0
1
0
1.800
0
1
0
1
1
1.825
NOTE: 0 = connected to GND, 1 = open or connected to 3.3V
through pull-up resistors
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s output
of the PWM converters. This generates PHASE pulses of
increasing width that charge the output capacitor(s). The
resulting output voltages start-up as shown in Figure 5.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval
and the surge current are programmed by the soft-start
capacitor, C_SS. Programming a faster soft-start interval
increases the peak surge current. Using the recommended
0.1µF soft start capacitors ensure all output voltages ramp
up to their set values in a quick and controlled fashion, while
meeting the system timing requirements.
Shutdown
Neither PWM output switches until the soft-start voltage
(V_SS) exceeds the oscillator’s valley voltage. Additionally,
the reference on each linear’s amplifier is clamped to the
soft-start voltage. Holding the SS24 pin low (with an open
drain or open collector signal) turns off regulators 1, 2 and 3.
Regulator 4 (MCH) will simply drop its output to the
intermediate soft-start level. This output is not allowed to
violate the 2V maximum potential gap to the ATX 3.3V
output.
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