ISL6523A Datasheet, PDF (5/16 Pages) Intersil Corporation – VRM8.5 Dual PWM and Dual Linear Power System Controller

ISL6523A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
LGATE Source
LGATE Sink
PROTECTION
VSEN1 Over-Voltage (VSEN1/DACOUT)
OCSET1,2 Current Source
Soft-Start Current
POWER GOOD
VSEN1 Upper Threshold
(VSEN1/DACOUT)
VSEN1 Under-Voltage
(VSEN1/DACOUT)
VSEN1 Hysteresis (VSEN1/DACOUT)
PGOOD Voltage Low
VSEN2 Under-Voltage
VSEN2 Hysteresis
VTTPG Voltage Low
NOTE:
2. Guaranteed by design
SYMBOL
I_LGATE
R_LGATE
TEST CONDITIONS
VCC = 12V, V_LGATE1 = 1V
V_LGATE = 1V
I_OCSET
I_SS13,24
VSEN1 Rising
V_OCSET = 4.5V_DC
V_SS13,24 = 2.0V_DC
VSEN1 Rising
VSEN1 Rising
V_PGOOD
V_VTTPG
VSEN1 Falling
I_PGOOD = -4mA
VSEN2 Rising
VSEN2 Falling
I_VTTPG = -4mA
MIN TYP MAX UNITS
-
1
-
A
-
1.4 3.0
Ω
-
120
-
%
170 200 230
µA
-
28
-
µA
108
-
110
%
92
-
94
%
-
2
-
%
-
-
0.8
V
- 1.00 -
V
-
60
-
mV
-
-
0.8
V
Typical Performance Curve
140
C_UGATE1 = C_UGATE2 = C_LGATE1 = C
120 ^VIN ^{= 5V}
V_CC = 12V
100
C = 4800pF
80
C = 3600pF
60
C = 1500pF
40
20
C = 660pF
0
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 4. BIAS SUPPLY CURRENT vs FREQUENCY
Functional Pin Descriptions
VCC (Pin 28)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
GND (Pin 17)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGND (Pin 24)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
VAUX (Pin 16)
Connect this pin to the ATX 3.3V output. The voltage present
at this pin is monitored for sequencing purposes. This pin
provides the necessary base bias for the NPN pass
transistors, as well as the current sunk through the 5kΩ VID
pull-up resistors.
SS13 (Pin 13)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the synchronous switching converter (V_OUT1) and
the AGP regulator (V_OUT3). A VTTPG high signal is also
delayed by the time interval required by the charging of this
capacitor from 0V to 1.25V (see Soft-Start details).
SS24 (Pin 12)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the soft-start
interval of the standard buck converter. Pulling this pin below
0.8V induces a chip reset (POR) and shutdown.
VTTPG (Pin 9)
VTTPG is an open collector output used to indicate the
status of the standard buck regulator output voltage. This pin
is pulled low when the output is below the under-voltage
threshold or when the SS13 pin is below 1.25V.
5