ISL6522B Datasheet, PDF (9/15 Pages) Intersil Corporation – Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller

ISL6522B
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C_SS
close to the SS pin because the internal current source is
only 10µA. Provide local V_CC decoupling between VCC and
GND pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins.
BOOT
D1
C_BOOT
ISL6522B
PHASE
SS
+12V
C_SS
GND
VCC
C_VCC
+V_IN
Q1 _LO
V_OUT
Q2 ^CO
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V_OUT) is regulated to the reference voltage level. The error
amplifier (error amp) output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
OSC
V_IN
DRIVER
PWM
COMPARATOR
L_O
∆V_OSC
-
+
DRIVER
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
PHASE
C_O
ESR
(PARASITIC)
V_OUT
DETAILED COMPENSATION COMPONENTS
C2
C1
R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
-
+
ISL6522B
FB
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
------------------¹--------------------
2π • L_O • C_O
F_ESR=
----------------------¹----------------------
2π • (ESR • C_O)
The compensation network consists of the error amplifier
(internal to the ISL6522B) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F_Z1
=
----------------¹------------------
2π • R2 • C1
F_P1
=
--------------------------¹----------------------------
2π
•
R
2
•


C^-C----1^{-1----+•-----CC----2-}2^{--}
F_Z2 = ₂----_π-----_•----₍---_R-----₁----+-¹----_R-----₃----₎---_•-----_C----₃--
F_P2
=
----------------¹------------------
2π • R3 • C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole
(~75% F_LC)
9