ISL6315_07 Datasheet, PDF (9/20 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6315
illustrated in the ISL6315’s block diagram. Just prior to the
upper drive turning the MOSFET on, the lower MOSFET
drive turns the freewheeling element off. The upper
MOSFET is kept on until the clock signals the beginning of
the next switching cycle and the PWM pulse is terminated.
CURRENT SENSING
ISL6315 senses current by sampling the voltage across the
lower MOSFET during its conduction interval. MOSFET
r_DS(ON) sensing is a no-added-cost method to sense current
for channel current balance and overcurrent protection.
The PHASE pins are used as inputs for each channel.
Internal circuitry samples the lower MOSFETs’ r_DS(ON)
voltage, once each cycle, during their conduction periods
and time multiplexes the sampled voltages across the ISEN
resistor. The current that is thus developed through the ISEN
resistor is duplicated and used for channel current balancing
and overcurrent detection.
CHANNEL-CURRENT BALANCE
Another benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this, the
designer avoids the complexity of driving multiple parallel
MOSFETs and the expense of using expensive heat sinks
and exotic magnetic materials.
In order to fully realize the thermal advantage, it is important
that each channel in a multiphase converter be controlled to
deliver about the same current at any load level. Intersil
multiphase controllers ensure current balance by comparing
each channel’s current to the average current delivered by
all channels and making appropriate adjustments to each
channel’s pulse width based on the error. The error signal
modifies the pulse width to correct any unbalance and force
the error toward zero.
OVERCURRENT PROTECTION
The individual channel currents, as sensed via the PHASE
pins and scaled via the ISEN resistor, are continuously
monitored and compared with an internal 95μA reference
current. If both channels’ currents exceed, at any time, the
reference current, the overcurrent comparator triggers an
overcurrent event. Similarly, an OC event is also triggered if
either channel’s current exceeds the 95μA reference for 7
consecutive switching cycles.
As a result of an OC event, output drives on both channels
turn off both upper and lower MOSFETs. The system then
waits in this state for a period of 4096 switching clock cycles.
The wait period is followed by a soft-start attempt. If the soft-
start attempt is successful, operation continues as normal.
Should the soft-start attempt fail, the ISL6315 repeats the
2048-cycle wait period and follows with another soft-start
attempt. This hiccup mode of operation continues indefinitely
(as depicted in Figure 4) for as long as the controller is
enabled or until the overcurrent condition is removed.
OUTPUT CURRENT
OUTPUT VOLTAGE
FIGURE 4. OVERCURRENT BEHAVIOR IN HICCUP MODE
OFFSET VOLTAGE PROGRAMMING
The OFS pin allows a user to program a small positive or
negative offset into the output voltage setting normally
determined by the 5-bit DAC. The offset input was
designed for small offset magnitudes, generally no larger
than +/-100mV. As the offset is created by injecting a
current into the FB pin, its magnitude is independent of the
DAC setting and the offset of the output voltage is not
detected by the internal monitoring blocks. In effect, offset
shifts the response level for OVP protection: for example, a
-50mV offset will cause the operating OVP threshold to be
reached when the output voltage reaches 150mV above
the DAC-set output voltage, instead of 200mV as it would
be the case with no offset programmed. The equation
presented in the OFS pin description holds true even if a
resistor divider is used at the FB to raise the output voltage
to a level above that set by the DAC.
OUTPUT VOLTAGE SETTING
The ISL6315 uses a digital to analog converter (DAC) to gen-
erate a reference voltage based on the logic signals at the VID
pins. The DAC decodes the 5 or 6-bit logic signals into one of
the discrete voltages shown in Tables 1 through 3. Each VID
pin is pulled up to an internal 1.2V voltage by weak current
sources (about 45μA current, decreasing to 0 as the voltage at
the VID pins varies from 0 to the internal 1.2V pull-up voltage).
External pull-up resistors or active-high output stages can aug-
ment the pull-up current sources, up to a voltage of 5V.
._{The ISL6315 accommodates three different DAC ranges:}
Intel VRM9.0, AMD Hammer, or Intel VRM10.0 - see
“Functional Pin Description” on page 5 for proper
connections for desired DAC range compatibility.
9
FN9222.1
July 18, 2007