ISL6315_07 Datasheet, PDF (6/20 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6315
sources; the internal pull-up current decrease to 0 as the VID
voltage approaches the internal pull-up voltage. All VID pins
are compatible with external pull-up voltages not exceeding
the IC’s bias voltage.
DACSEL/VID5 (Pin 3)
If VRM10 pin is grounded, DACSEL/VID5 represents the 6th
voltage identification input from the VRM10-compliant
microprocessor, otherwise known as VID5. If VRM10 pin is
open or pulled high, DACSEL/VID5 selects the compliance
standard for the internal DAC: pulled to ground it encodes the
DAC with AMD Hammer VID codes, while left open or pulled
high, it encodes the DAC with Intel VRM9.0 codes.
VRM10 (Pin 4)
This pin selects VRM10.0 DAC compliance when grounded.
Left open, it allows selection of either VRM9.0 or Hammer
DAC compliance via DACSEL pin.
ENLL (Pin 21)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Held low, this pin disables controller operation. Pulled
high, the pin enables the controller for operation.
FB and COMP (Pins 6, 5)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator’s feedback loop.
An internal current source injects the offset (OFS) current
sampled into the FB pin. Pulling COMP to ground through an
impedance lower than 15Ω disables the controller (same
effect as ENLL pulled low).
ISEN (Pin 7)
This pin is used to close the current-balance loop and set the
overcurrent protection threshold. A resistor connected
between this pin and VCC has a voltage drop forced across
it equal to that sampled across the lower MOSFET’s r_DS(ON)
during approximately the middle of its conduction interval.
The resulting current through this resistor is used for channel
current balancing and overcurrent protection. The voltage
across the R_ISEN resistor is time multiplexed between the
two channels.
Use the following equation to select the proper R_ISEN
resistor:
R_ISEN
=
-^r--^D----^S----⁽--^O----^N-----⁾--^M-----^A---^X-----^×-----^I--^O-----^U----^T-
95 μ A
(EQ. 1)
where:
r_DS(ON)MAX = lower MOSFET’s highest drain-source ON
resistance (Ω; include temperature effects)
I_OUT = channel maximum output current (A)
Read “Channel Balance Current Loop” on page 7 paragraph
for more information.
UGATE1, 2 (Pins 19, 12)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.
BOOT1, 2 (Pins 20, 11)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
PHASE1, 2 (Pins 18, 13)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives.
LGATE1, 2 (Pins 17, 15)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates.
OFS (Pin 9)
This pin is used to create an adjustable output voltage offset.
For no offset, leave this pin open. For negative offset, connect
a R’_OFS resistor from this pin to VCC and size it according to
the following equation:
R′_OFS
=
R₁
×
-------¹----⁵---⁰---⁰---------
V_OFFSET
(EQ. 2)
where:
V_OFFSET = desired output voltage offset magnitude (mV)
For positive output voltage offset, connect a R_OFS resistor
from this pin to GND, sizing it according to the following
equation:
R_OFS
=
R₁
×
---------⁵---⁰----⁰----------
V_OFFSET
(EQ. 3)
For more information, refer to the ‘Output Voltage Offset
Programming’ paragraph.
SSEND (Pin 10)
This pin is an end of Soft-Start (SS) indicator; open drain
output device stays ON during soft-start, and goes open when
soft-start ends.
6
FN9222.1
July 18, 2007