ISL6271A_15 Datasheet, PDF (9/17 Pages) Intersil Corporation – Integrated XScale Regulator

ISL6271A
TABLE 2. SLEW RATE-SET BIT
I²C DATA BYTE
D5 D4
XX0 0XXXX
XX0 1XXXX
XX1 0XXXX
XX1 1XXXX
RATE
mV/µs
0.5
1
2.5
5
Soft-Start and Slew Rate Control
To assure stability and minimize overshoot at start-up and
during DVM transitions, the ISL6271A implements a
controlled rise time of each regulator output. The Slew Rate
control bits in Table 2 are used to route one of 4 current
sources to the SOFT pin. These current sources along with
the soft-start capacitor will control the rate of rise of voltage
during DVM transitions. The recommended 10nF soft-start
capacitor will result in a typical slew rate of 1mV/µs at start-
up and the programmable DVM slew rates defined in
Table 2. Slower or faster start-up and DVM transactions can
be accommodated by selecting a smaller or larger soft-start
capacitor. By default bits D5 and D4 are set to “01”
corresponding to a SS current of 10µA. Writing “00” will
result in a 5µA of current whereas “10” corresponds to 24µA
and “11” corresponds to a typical source current of 47µA.
The expression i = cdv/dt can be used to solve for the
appropriate slew rate.
Example: Desired slew rate = 10mV/µs fixed slew rate and
the slew rate control bits are set to “11”. Then:
Isource = I₁₁= 47µA (nominal), therefore
C= ^I---^s---^o--_d--d--^u_----v--t--^r--^c----^e- = -_1-⁴------₀--⁷_------_m-^_-s------^A--_V------ = 4.7nF
(EQ. 1)
NOTE: Intel specifies a maximum slew rate for Vcore transitions. To
satisfy this requirement, the SS capacitor and SOFT pin sink/source
current tolerances must be considered. Refer to the Electrical
Specification table and appropriate Intel documents for details. Note
that when D5 and D4 are set to “11” the maximum source current is
64µA. Under this condition, the slew rate would be 16mV/µs if a
4.7nF SS capacitor varied by 15% negative. For this reason a 6.8nF
capacitor is recommended when D5 and D4 are set to “11”.
Undervoltage and Overvoltage on Vout
If the output voltage of the switching regulator exceeds 114%
of the SOFT pin voltage (programmed DAC voltage) for
longer than 1.5µs, an overvoltage fault will be tripped and
the phase node will be three-stated. Hysteresis requires the
voltage to fall to 106% before the fault is automatically reset.
An undervoltage occurs when the output voltage falls below
86% of SOFT pin voltage. Once this fault is triggered,
hysteresis sets the reset point to 94%. An undervoltage
condition will occur if the output DC current plus the ripple
exceeds the current limit point for a period longer than the
output capacitance hold-up time.
Loop Compensation
All three regulators are internally compensated for stability;
however, an external resistor connected between the core
regulator output and the FB pin can be used to alter the
closed loop gain of the switching regulator and optimize
transient response for a given output filter selection. The
following combinations of component values are
recommended:
TABLE 3. RECOMMENDED KEY COMPONENT VALUES FOR
CORE REGULATOR
LO
COUT
RCOMP
3.3µH
4.7µF
100k
4.7µH
10µF
50k
Overcurrent Limit
To protect against an overcurrent condition, the core
regulator employs a proprietary current sensing circuit that
monitors the voltage drop across the internal upper
MOSFET. When an overcurrent condition is detected the
controller will limit the output current and if the condition
persists, the output voltage level will drop below the
undervoltage level tripping the PGOOD indicator. See
“Applications section” for details.
SRAM and PLL LDOs
The two linear regulators on the ISL6271A are designed to
satisfy the power requirements of the SRAM and phase-lock
loop circuitry internal to XScale processors. These
regulators share a common input voltage pin (LVCC) that
can be tied to the main battery PVCC or preferably to a lower
system voltage to effect a higher conversion efficiency. It is
recommended that LVCC be connected to pre-regulated
voltages between 1.8V - 2.5V.
Each LDO is internally compensated and designed to
operate with a low-ESR ceramic capacitor (X5R or better)
between 2.2µF and 3.3µF. Both LDOs have overcurrent,
undervoltage and thermal protection and share a common
enable signal (EN) with the core regulator, allowing them to
be enabled/disabled together as required by the processor.
BFLT#
The logic state of the BFLT# output indicates whether the
main battery input is adequate to power the system in
normal operation. A battery low (or absent) condition is
indicated by this pin being pulled low. Upon initial application
of battery power, it will indicate a battery good condition
when the battery voltage is greater than 2.8V (nominal), and
it will sustain the battery good indication until the voltage
drops below 2.6V (nominal). The output is pulled actively
low, with no main battery connected by tapping power from
the secondary input, BBAT. It is actively driven to BBAT
when the main battery is within the POR thresholds.
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9
FN9171.2
August 10, 2015