ISL6271A_15 Datasheet, PDF (12/17 Pages) Intersil Corporation – Integrated XScale Regulator

ISL6271A
Loop stability calculations are simplified when using the
ISL6271A and are limited to the selection of a single
feedback resistor, Rcomp. The Rcomp resistor will affect the
closed loop gain of the internal compensation network as in
Equation 2. Empirical and theoretical testing suggests that a
value of 50K will provide the most ideal transient response to
the expected XScale load and voltage transitions when used
with the recommended 4.7µH output inductor and 10µF
output capacitor. Using the ISL6271A evaluation board, a
50K feedback resistor resulted in a minimum of 60 degrees
of phase margin under worst case line and load transitions.
When placing the Rcomp feedback resistor, be sure to avoid
routing it parallel to switching circuits, especially the phase
node, that could otherwise induce noise into the FB pin.
Gcomp = ^-_R--^R---_c--^c-_o---^-_m---^C---_p--^c---_--^--_C--^s---_c--+--_--¹--_s---^
(EQ. 2)
Overcurrent Protection and Ripple Current
The OCL trip level inside the ISL6271A is a function of the
upper PMOS output transistor’s on-resistance and over-
current comparator threshold voltage. The device was
designed to accommodate a maximum RMS current of
800mA, and to accommodate this DC current level plus the
associated ripple current, the OC limit of the ISL6271A will
not trip below 950mA. Ripple current inside the ISL6271A is
defined by the expression,
Iripple = ^---^V----ⁱ--ⁿ--_L---–-_----^V-_f--_s-^o----^u----^t--^  ^V---_V--^o--_i--^un----^t
(EQ. 3)
where “fs” is the switching frequency of the converter. The
architecture of the ISL6271A is such that the switching
frequency will increase with higher input voltage. This
behavior attempts to keep the ripple current constant for a
given output inductor, input voltage and output voltage. To
minimize ripple current and preserve transient response,
Intersil recommends an output inductor between 3.3µH and
4.7µH. Higher values of inductance will minimize the risk of
tripling the over-current minimum threshold of 950mA.
SSR Theoretical Operation
The ISL6271A is a PWM controller that uses a novel
architecture developed by Intersil called Synthetic Ripple
Regulation. The architecture operates similar to a hysteretic
converter without the deficiencies of noise sensitivities.
Reduced to its simplest form, the Synthetic Ripple Regulator
inside the ISL6271A is made up of three elements as
illustrated in Figure 20: A transconductance amplifier
(Rippler Amplifier), a window comparator with hysteresis and
an Error Amplifier. While operating in continuous conduction
mode, the converter has a natural switching frequency of
1.2MHz delivering an ultra low output voltage ripple and
exceptional transient response as illustrated in Figures 23
and 24.
SYNTHETIC RIPPLE REGULATION
SIMPLIFIED DIAGRAM
ERROR AMP
Vref(DAC) ₊
-
WINDOW COMPARATOR
+
-
Rc Cc
SINK/SOURCE
CONTROL
RIPPLE CAPACITOR
VOLTAGE
Gm AMP
+-
toff ton
{ ^Cr
Iout =
Gm Vout ,off
Gm (Vin-Vout ),on
INPUT VOLTAGE
Lo
OUTPUT
VOLTAGE
Rcomp
FIGURE 20. SIMPLIFIED SRR DIAGRAM
Figure 20 illustrates the two control loops inherent to the
SRR architecture. The inner loop consists of the ripple
amplifier, the window comparator, gate drive circuitry and the
power stage. The outer loop controls the inner loop and is
made up a high bandwidth error amplifier with internal and
external compensation.
CCM Operation - Heavy Current
Figure 21 illustrates the SSR in CCM. When the upper
P-MOSFET is turned on, the phase voltage equals the input
voltage and the ripple transconductance amplifier outputs a
current proportional to the difference of the input and output
voltage. This current will ramp the voltage on the ripple
capacitor Cr in Figure 20. As this voltage reaches the upper
threshold of the hysteretic comparator, the comparator
output will switch low. After a propagation delay, the upper
P-MOSFET is turned off and the lower N-MOSFET is turned
on, forcing synchronous rectification. At this point, the ripple
amplifier now has inputs of 0V and VOUT and will sink
current to discharge the ripple capacitor. When the voltage
across the ripple capacitor reaches the lower threshold of
the hysteresis window, the window comparator outputs a
high signal. After a propagation delay, the upper P-MOSFET
turns on repeating the previous switching cycle.
PHASE
VOLTAGE
VOUT
VRP
HYSTERESIS
WINDOW
FIGURE 21. SYNTHETIC RIPPLE REGULATION IN CCM
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FN9171.2
August 10, 2015