ISL6271A_15 Datasheet, PDF (15/17 Pages) Intersil Corporation – Integrated XScale Regulator

ISL6271A
Internal ESD Structures
The ISL6271A input/output pins are protected from over-
voltage conditions by clamping the pin to one diode drop
above or below the VCC voltage rail. During shutdown it is
possible that the SDA and SCL pins have a voltage greater
than VCC. Under this condition, the ESD diodes will provide
a reverse current path to circuitry on VCC that can act as a
load on the back-up battery. To avoid this condition, interrupt
VCC from external circuitry if a voltage greater than VCC is
expected on any of the pins identified below.
PGND
BBAT
VCC
GND
GND
GND
Layout Recommendation
LDO
OUTPUT
CAPS
SINGLE
PT. GND
FB RES
OUTPUT CAP
OUTPUT
INDUCTOR
5x5x1mm
SOFT-START
CAP
VCC LPF
PVCC INPUT CAP
FIGURE 27. COMPONENT PLACEMENT AND TOP COPPER
SDA
PVCC
SCL
LVCC
EN
VOUT
VPLL
FB
VSRAM
PGOOD
SOFT
BFLT#
FIGURE 26. INTERNAL ESD STRUCTURES
Since the ISL6271A can operate at a high switching
frequency, it is especially important to apply good layout
practices. Decoupling of the regulator’s input voltage
(PVCC) and minimizing the loop area associated with the
phase node output filter is essential for reliable operation.
Return currents from the load should find a low impedance
path to the PGND pin on the IC (Pin 8). Ideally, the core
voltage would be distributed to the embedded processor on
a low impedance power plane; however, a 30-50mil, short
trace should be sufficient. When implementing DVM it is
important to minimize inductance between the load and the
output filter. The processors can command slew rates of up
to 200mA/ns and local decoupling at the processor socket is
essential to satisfying this requirement.
References
[1] ISL6292 data sheet - Battery Charger
[2] EL7536 data sheet - System regulator
[3] C-Code examples for PWR_I2C bus communication -
Intersil support documentation available upon request.
[4] PHILLIPS I²C BUS Specification
[5] http://www.semiconductors.philips.com/buses/i2c/
[6] Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLF Packages”
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FN9171.2
August 10, 2015