ISL6268 Datasheet, PDF (9/14 Pages) Intersil Corporation – High-Performance Notebook PWM Controller

ISL6268
the PHASE and GND pins is nulled by the voltage dropped
across R_SEN as I_SEN conducts through it. An OCP fault
occurs if I_SEN rises above the OCP threshold current I_OC
while attempting to null the negative voltage across the
PHASE and GND pins. I_SEN must exceed I_OC on all the
PWM pulses that occur within 20µs. If I_SEN falls below I_OC
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when I_SEN
exceeds twice I_OC. The relationship between I_D and I_SEN is
written as:
I_SEN • R_SEN = I_D • r_DS(on)
(EQ. 3)
The value of R_SEN is then written as:
R_SEN
=
-^⎝⎛--^I--^F----^L----+-----^{I----P--2------P-----⎠⎞}----^•---^O-----^C-----^S----^P----^•---^r--^D----^S----⁽--^o---ⁿ----⁾
I_OC
(EQ. 4)
where:
- R_SEN (Ω) is the resistor used to program the overcurrent
setpoint
- I_SEN is the current sense current that is sourced from the
ISEN pin
- I_OC is the I_SEN threshold current sourced from the ISEN
pin that will activate the OCP circuit
- I_FL is the maximum continuous DC load current
- I_PP is the inductor peak-to-peak ripple current
- OC_SP is the desired overcurrent setpoint expressed as a
multiplier relative to I_FL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull
down to 63Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V_ENTHF or if V_CC has decayed
below the falling POR threshold voltage ^V_{VCC_THF}.
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold V_OVR. After the converter has
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off in response to the output voltage transversing the
V_OVR and V_OVF thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95Ω and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V_ENTHF or if V_CC has decayed below the
falling POR threshold voltage ^V_{VCC_THF}. The UVP fault
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold V_UV.
Over-Temperature
When the temperature of the ISL6268 increases above the
rising threshold temperature T_OTR, the IC will enter an OTP
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T_OTHYS at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V_ENTHF or if
V_CC decays below the falling POR threshold voltage
V_{VCC_THF. All other protection circuits function normally}
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold V_UV;
the PGOOD pin will pull down to 95Ω and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V_ENTHF or if V_CC has decayed below the falling POR
threshold voltage ^V_{VCC_THF}.
Programming the Output Voltage
When the converter is in regulation there will be 600mV from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the
GND pin when the converter is regulating at the desired
output voltage. The output voltage can be programmed from
600mV to 3.3V.
Programming the output voltage is written as:
V_REF
=
V
O
U
T
•
------------^R----^B----^O-----^T---^T----^O----^M---------------
R_TOP + R_BOTTOM
(EQ. 5)
where:
- V_OUT is the desired output voltage of the converter
- V_REF is the voltage that the converter regulates to
between the FB pin and the GND pin
- R_TOP is the voltage-programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop
compensation network
- R_BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Beginning with R_TOP between 1kΩ to 5kΩ, calculating
R_BOTTOM is written as:
R_BOTTOM
=
--^V----^R----^E----^F----^•---^R----^T----^O-----^P---
V_OUT – V_REF
(EQ. 6)
9
FN6348.0
August 22, 2006