ISL6268 Datasheet, PDF (7/14 Pages) Intersil Corporation – High-Performance Notebook PWM Controller

ISL6268
Theory of Operation
Modulator
The ISL6268 is a hybrid of fixed frequency PWM control, and
variable frequency hysteretic control. Intersil’s R³ technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust Ripple
Regulator” refers to the converter output inductor ripple
current, not the converter output ripple voltage. The R³
modulator synthesizes an AC signal V_R, which is an ideal
representation of the output inductor ripple current. The
duty-cycle of V_R is the result of charge and discharge
current through a ripple capacitor C_R. The current through
C_R is provided by a transconductance amplifier g_m that
measures the VIN and VO pin voltages. The positive slope
of V_R can be written as:
V_RPOS = (g_m) • (V_IN – V_OUT)
(EQ. 1)
The negative slope of V_R can be written as:
V_RNEG = g_m ⋅ V_OUT
(EQ. 2)
where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is set by a resistor connected across the FSET and GND
pins. The V_R, V_COMP, and V_W signals feed into a window
comparator in which V_COMP is the lower threshold voltage
and V_W is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as V_R traverses the V_W and
V_COMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V_R; the PWM switching frequency is inversely
proportional to the voltage between V_W and V_COMP.
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
Power-On Reset
The ISL6268 is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) V_CCR
threshold voltage. The controller will become once again
disabled when the voltage at the VCC pin decreases below
the falling POR V_CCF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6268 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage V_ENTHR the PGOOD
Soft-Start Delay T_SS begins and the output voltage begins to
rise. The output voltage enters regulation in approximately
1.5ms and the PGOOD pin goes to high impedance once T_SS
has elapsed.
1.5ms
VOUT
VCC and PVCC
EN
PGOOD
2.75ms
FIGURE 3. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if V_CC has not reached the rising POR
threshold V_CCR, or if V_CC is below the falling POR threshold
V_CCF. The ISL6268 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During
soft-start or if an undervoltage fault occurs, the PGOOD
pull-down resistance is 95Ω, or 32Ω for an overcurrent fault,
or 63Ω for an overvoltage fault.
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
7
FN6348.0
August 22, 2006