ISL6263C Datasheet, PDF (9/18 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator with Current Monitor for GPU Core Power

ISL6263C
Theory of Operation
The R³ Modulator
The heart of the ISL6263C is Intersil’s Robust-Ripple-
Regulator (R³) Technology™. The R³ modulator is a hybrid
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V_R that
appears across the internal ripple-capacitor C_R. The V_R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V_SOFT, together produce the voltage-ripple signal V_R.
A voltage window signal V_W is created across the VW and
COMP pins by sourcing a current proportional to g_mV_SOFT
through a parallel network consisting of resistor R_FSET and
capacitor C_FSET. The synthesized voltage-ripple signal V_R
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V_W and V_COMP. Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263C to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6263C has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
Voltage Programming
The output voltage V_OUT is regulated to the SOFT pin
voltage, V_SOFT, which is determined by the DAC output. The
DAC output voltage is programmed by the external five VID
pins. Refer to Table 1 for the VID voltage programming
specification.
Power-On Reset
The ISL6263C is disabled until the voltage at the VDD pin
has increased above the rising VDD power-on reset (POR)
V_{DD_THR} threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR V_{DD_THF} threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263C start-up timing. Once VDD
has ramped above V_{DD_THR}, the controller can be enabled
by pulling the VR_ON pin voltage above the input-high
threshold V_{VR_ONH}. Approximately 100µs later, the soft-start
capacitor C_SOFT begins slewing to the designated VID
set-point as it is charged by the soft-start current source I_SS.
The V_OUT output voltage of the converter follows the V_SOFT
voltage ramp to within 10% of the VID set-point then counts
GPU
MODE
TABLE 1. VID AND DAC TRUTH TABLE
V_SOFT
VID4 VID3 VID2 VID1 VID0 (DAC) (V)
-
-
-
-
-
0
0
0
0
0
0
1.28750
0
0
0
0
1
1.26175
0
0
0
1
0
1.23600
0
0
0
1
1
1.21025
0
0
1
0
0
1.18450
0
0
1
0
1
1.15875
0
0
1
1
0
1.13300
0
0
1
1
1
1.10725
0
1
0
0
0
1.08150
0
1
0
0
1
1.05575
0
1
0
1
0
1.03000
0
1
0
1
1
1.00425
0
1
1
0
0
0.97850
0
1
1
0
1
0.95275
0
1
1
1
0
0.92700
0
1
1
1
1
0.90125
1
0
0
0
0
0.87550
1
0
0
0
1
0.84975
1
0
0
1
0
0.82400
1
0
0
1
1
0.79825
1
0
1
0
0
0.77250
1
0
1
0
1
0.74675
1
0
1
1
0
0.72100
1
0
1
1
1
0.69525
1
1
0
0
0
0.66950
1
1
0
0
1
0.64375
1
1
0
1
0
0.61800
1
1
0
1
1
0.59225
1
1
1
0
0
0.56650
1
1
1
0
1
0.54075
1
1
1
1
0
0.51500
1
1
1
1
1
0.41200
13 switching cycles, then changes the open-drain output of
the PGOOD pin to high impedance. During soft-start, the
regulator always operates in continuous conduction mode
(CCM).
9
FN6745.1
July 8, 2010