ISL6263C Datasheet, PDF (11/18 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator with Current Monitor for GPU Core Power

ISL6263C
High Efficiency Diode Emulation Mode
The ISL6263C operates in continuous-conduction-mode
(CCM) during heavy load for minimum conduction loss by
forcing the low-side MOSFET to operate as a synchronous
rectifier. An improvement in light-load efficiency is achieved
by allowing the converter to operate in diode-emulation
mode (DEM) where the low-side MOSFET behaves as a
smart-diode, forcing the device to block negative inductor
current flow.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current flows into the
source of the high-side MOSFET, or into the drain of the
low-side MOSFET. When the low-side MOSFET conducts
positive inductor current, the phase voltage will be negative
with respect to the VSS pin. Conversely, when the low-side
MOSFET conducts negative inductor current, the phase
voltage will be positive with respect to the VSS pin. Negative
inductor current occurs when the output DC load current is
less than ½ the inductor ripple current. Sinking negative
inductor current through the low-side MOSFET lowers
efficiency through unnecessary conduction losses. Efficiency
can be further improved with a reduction of unnecessary
switching losses by reducing the PWM frequency. The PWM
frequency can be configured to automatically make a
step-reduction upon entering DEM by forcing a
step-increase of the window voltage V_W. The window
voltage can be configured to increase approximately 30%,
50%, or not at all. The characteristic PWM frequency
reduction, coincident with decreasing load, is accelerated by
the step-increase of the window voltage.
The converter will enter DEM after detecting three
consecutive PWM pulses with negative inductor current. The
negative inductor current is detected during the time that the
high-side MOSFET gate driver output UGATE is low, with the
exception of a brief blanking period. The voltage between
the PHASE pin and VSS pin is monitored by a comparator
that latches upon detection of positive phase voltage. The
converter will return to CCM after detecting three
consecutive PWM pulses with positive inductor current.
The inductor current is considered positive if the phase
comparator has not been latched while UGATE is low.
Because the switching frequency in DEM is a function of
load current, very light load condition can produce
frequencies well into the audio band. To eliminate this
audible noise, an audio filter can be enabled that briefly turns
on the low-side MOSFET gate driver LGATE approximately
every 35µs.
The DEM and audio filter operation are programmed by the
AF_EN and FDE pins in conjunction with VID0:VID4
according to Table 2.
TABLE 2. DIODE EMULATION MODE and AUDIO FILTER
GPU MODE
DEM VOLTAGE AUDIO
(VID code) FDE AF_EN STATUS WINDOW FILTER
0
- DISABLED NOM
-
MODE 1
1
- ENABLED 130% NOM
-
-
0 ENABLED 150% NOM
-
MODE 2
1
1 ENABLED 130% NOM
-
0
1 ENABLED 130% NOM ENABLED
Smooth mode transitions are facilitated by the R³ modulator,
which correctly maintains the internally synthesized ripple
current information throughout mode transitions.
Current Monitor
The ISL6263C features a current monitor output. The
voltage between the IMON and VSS pins is proportional to
the output inductor current. The output inductor current is
proportional to the voltage between the ICOMP and VO pins.
The IMON pin has source and sink capability for close
tracking of transient current events. The current monitor
output is expressed in Equation 1:
V_IMON = (V_ICOMP – V_O) ⋅ 31
(EQ. 1)
Protection
The ISL6263C provides overcurrent protection (OCP),
overvoltage protection (OVP), and undervoltage protection
(UVP), as shown in Table 3.
Overcurrent protection is tied to the current sense amplifier.
Given the overcurrent set point I_OC, the maximum voltage
at ICOMP pin V_ICOMP(max) (which is the voltage when
OCP happens) can be determined by the current sense
network (explained in “Inductor DCR Current Sense” on
page 14 and “Resistor Current Sense” on page 15). During
start-up, the ICOMP pin must fall 25mV below the OCSET
pin to reset the overcurrent comparator, which requires
(V_ICOMP(max) - V_O) > 25mV.
The OCP threshold detector is checked every 15µs and will
increment a counter if the OCP threshold is exceeded,
conversely the counter will be decremented if the load
current is below the OCP threshold. The counter will latch an
OCP fault when the counter reaches eight. The fastest OCP
response for overcurrent levels that are no more than 2.5
times the OCP threshold is 120µs, which is eight counts at
15µs each. The ISL6263C protects against hard shorts by
latching an OCP fault within 2µs for overcurrent levels
exceeding 2.5 times the OCP threshold.
The overcurrent threshold is determined by the resistor
R_OCSET between OCSET pin and VO pin. The value of
R_OCSET is calculated in Equation 2:
R_OCSET = -^V----^I--^C----^O----^M----₁-^P---₀-⁽--^m-_μ---_A-^a---^x---⁾---–-----^V----^O---
(EQ. 2)
11
FN6745.1
July 8, 2010