ISL6219A_07 Datasheet, PDF (9/17 Pages) Intersil Corporation – Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications

ISL6219A
V_COMP
+
-
f(jω)
+
-
SAWTOOTH SIGNAL
I_ER
I_{AVG ÷ N}
Σ
-
+
PWM1
I₃
I₂
I₁
FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able
to cool more effectively than the other(s) due to nearby air
flow or heat sinking components. The other channel(s) may
have more difficulty cooling with comparatively less air flow
and heat sinking. The hotter channels may also be located
close to other heat-generating components tending to drive
their temperature even higher. In these cases, a proper
selection of the current sense resistors (R_ISEN in Figure 4)
introduces channel current unbalance into the system.
Increasing the value of R_ISEN in the cooler channels and
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
OVERCURRENT PROTECTION
The average current, I_AVG in Figure 5, is continually
compared with a constant 75μA reference current. If the
average current at any time exceeds the reference current,
the comparator triggers the converter to shut down. All PWM
signals are placed in a high-impedance state which signals
the drivers to turn off both upper and lower MOSFETs. The
system remains in this state while the controller counts 2048
phase-clock cycles.
This is followed by a soft-start attempt (see Soft-Start). If the
soft-start attempt is successful, operation will continue as
normal. Should the soft-start attempt fail, the ISL6219A
repeats the 2048-cycle wait period and follows with another
soft-start attempt. This hiccup mode of operation continues
indefinitely as shown in Figure 6 as long as the controller is
enabled or until the overcurrent condition resolves.
VOLTAGE REGULATION
The ISL6219A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
pins VID4 to VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1. Each
VID input offers a 20mA pull up to 2.5V for use with open-
drain outputs. External pull-up resistors or active-high output-
stages can augment the pull-up current sources, but a slight
accuracy error can occur if they are pulled above 2.9V.
9
OUTPUT CURRENT, 20A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
5ms/DIV
FIGURE 6. OVERCURRENT BEHAVIOR IN HICCUP MODE
The integrating compensation network shown in Figure 7
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the error amplifier. Intersil
specifies the guaranteed tolerance of the ISL6219A to
include all variations in the amplifiers and reference so that
the output voltage remains within the specified system
tolerance.
EXTERNAL CIRCUIT
R_C
C_C
COMP
ISL6219A INTERNAL CIRCUIT
ERROR AMPLIFIER
FB
-
R_FB
+
V_DROOP
-
I_AVG
+
V_COMP
REFERENCE
VOLTAGE(V_DAC)
VSEN
V_OUT
FIGURE 7. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
FN9093.1
March 20, 2007