ISL6219A_07 Datasheet, PDF (11/17 Pages) Intersil Corporation – Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications

ISL6219A
1.23V
+
-
VCC
EXTERNAL CIRCUIT
-
+ _FS/EN
S1
ENABLE
SIGNAL
FIGURE 8. EXTERNAL ENABLE SIGNAL CIRCUIT
The frequency select/enable input (FS/EN) has a 1V threshold
which must be exceeded before the internal oscillator begins
running. An external enable signal should be used to control the
gate of an external MOSFET tied to the FS/EN pin, see Figure
8. This MOSFET must pull FS/EN below the 1V threshold to
disable the controller. When enabling the controller, this
external enable circuit must release the FS/EN pin to float to the
designed 1.23V level.
The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shut-down
mode after receiving this code and will start up upon
receiving any other code.
To enable the controller, VCC must be greater than the POR
threshold; FS/EN must be greater than 1V; and VID cannot
be equal to 11111. Once these conditions are true, the
controller immediately initiates a soft start sequence.
SOFT-START
After the POR function is completed with V_CC reaching
4.38V, the soft-start sequence is initiated. Soft-Start, by its
slow rise of CORE voltage from zero, avoids an over-current
condition by slowly charging the output capacitors. This
voltage rise is initiated by an internal DAC that slowly raises
the reference voltage to the error amplifier input. The voltage
rise is controlled by the oscillator frequency and the DAC
within the controller, therefore, the output voltage is
effectively regulated as it rises to the final programmed
CORE voltage value.
For the first 32 PWM switching cycles, the DAC output
remains inhibited and the PWM outputs remain in a
high-impedance state. From the 33rd cycle and for another,
approximately 150 cycles the PWM output remains low,
clamping the lower output MOSFETs to ground. The time
variability is due to the error amplifier, sawtooth generator and
comparators moving into their active regions. After this short
interval, the PWM outputs are enabled and increment the
PWM pulse width from zero duty cycle to operational pulse
width, thus allowing the output voltage to slowly reach the
CORE voltage. The CORE voltage will reach its programmed
value before the 2048 cycles, but the PGOOD output will not
be initiated until the 2048th PWM switching cycle.
The soft-start time, t_SS, is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
example, a converter switching at 300kHz has a soft-start
time of :
T_SS
=
-²----¹---¹--
f_SW
=
-----²---⁰---⁴----⁸------
300 k H z
=
6.8 m s
(EQ. 5)
Figure 9 shows the waveforms when the regulator is
operating at 300kHz. Note that the soft-start duration is a
function of the Channel Frequency as explained previously.
DYNAMIC VID
The ISL6219A is capable of executing on-the-fly
output-voltage changes. At the beginning of the phase-1
switching cycle (defined in the section entitled PWM
Operation), the ISL6219A checks for a change in the VID
code. The VID code is the bit pattern present at pins
VID4-VID0 as outlined in Voltage Regulation. If the new
code remains stable for another full cycle, the ISL6219A
begins incrementing the reference by making 25mV change
every two switching cycles until it reaches the new VID code.
Since the ISL6219A recognizes VID-code changes only at
the beginning of a switching cycle, up to one full cycle may
pass before a VID change registers. This is followed by a
one-cycle wait before the output voltage begins to change.
Thus, the total time required for a VID change, t_DV, is
dependent on the switching frequency (f_S), the size of the
change (ΔV_ID), and the time before the next switching cycle
begins. The one-cycle uncertainty in Equation 6 is due to the
possibility that the VID code change may occur up to one full
cycle before being recognized. The time required for a
converter running with f_S = 500kHz to make a 1.5V to 1.7V
reference-voltage change is between 30μs and 32μs as
calculated using Equation 6. This example is also illustrated
in Figure 10.
SS Interval
V_COMP, 1V/div
0V
VCORE, 1V/div
0V
FS/EN, 2V/div
0V
PGOOD, 5V/div
0V
1ms/div
FIGURE 9. START-UP OF 3 PHASE SYSTEM OPERATING AT
300kHz
11
FN9093.1
March 20, 2007