ISL5740 Datasheet, PDF (9/12 Pages) Intersil Corporation – 3V Dual 10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference

ISL5740
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
+Full Scale (+f_S) -¹/₄LSB
+f_S - 1¹/₄LSB
+³/₄ LSB
-¹/₄ LSB
-f_S + 1³/₄LSB
-Full Scale (-f_S) + ³/₄LSB
DIFFERENTIAL INPUT
VOLTAGE
(I/Q_IN+ - I/Q_IN-)
0.499756V
0.498779V
732.422µV
-244.141µV
-0.498291V
-0.499268V
OFFSET BINARY OUTPUT CODE
MSB
LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
NOTE:
8. The voltages listed above represent the ideal center of each output code shown with V_REFIN = +1.25V.
Detailed Description
Theory of Operation
The ISL5740 is a dual 10-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front end differential-in-differential-
out sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a non-
overlapping two phase signal, Φ₁ and Φ₂, derived from the
master sampling clock. During the sampling phase, Φ₁, the
input signal is applied to the sampling capacitors, C_S. At the
same time the holding capacitors, C_H, are discharged to
analog ground. At the falling edge of Φ₁ the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, Φ₂, the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between C_S and C_H completing one
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
hold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the I/Q_IN pins see only the on-resistance of a
switch and C_S. The relatively small values of these
components result in a typical full power input bandwidth of
400MHz for the converter.
I/Q_IN+
I/Q_IN-
Φ₁
Φ₂
Φ₁
Φ₁
C_S
C_S
Φ₁
C_H
-+
+-
C_H
Φ₁
V_OUT+
V_OUT-
Φ₁
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the Functional Block Diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
3-9