English
Language : 

ISL32601EFBZ Datasheet, PDF (9/23 Pages) Intersil Corporation – 1.8V to 3.3V, Micro-Power, ±15kV ESD, +125°C, Slew Rate Limited, RS-485/RS-422 Transceivers
ISL32600E, ISL32601E, ISL32602E, ISL32603E
Electrical Specifications ISL32602E, ISL32603E: Test Conditions: VCC = 1.8V to 3.6V; Typicals are at VCC = 1.8V,
TA = +25°C; Unless Otherwise Specified. Boldface limits apply over the operating temperature range. (Note 6) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 15) TYP (Note 15) UNITS
SWITCHING CHARACTERISTICS
Maximum Data Rate
Driver Differential Output Delay
Driver Differential Output Skew
Driver Differential Rise or Fall Time
Driver Enable to Output High
fMAX
tDD
tSKEW
tR, tF
tZH
(Figures 6, 7)
VCC = 1.8V, RDIFF = ∞
VCC ≥ 3V, RDIFF = 54Ω
CD = 50pF (Figure 4) VCC = 1.8V, RDIFF = ∞
VCC ≥ 3V, RDIFF = 54Ω
CD = 50pF (Figure 4) VCC = 1.8V, RDIFF = ∞
VCC ≥ 3V, RDIFF = 54Ω
CD = 50pF (Figure 4) VCC = 1.8V, RDIFF = ∞
VCC ≥ 3V, RDIFF = 54Ω
RL = 1kΩ, CL = 50pF, SW = GND (Figure 5),
(Note 9)
Full 256
-
-
kbps
Full 460
-
-
kbps
Full
-
750 2600 ns
Full
-
350 1500 ns
Full
-
120 220
ns
Full
-
2
100
ns
Full 150 1700 4500 ns
Full 200 400 900
ns
Full
-
-
3000 ns
Driver Enable to Output Low
tZL
RL = 1kΩ, CL = 50pF, SW = VCC (Figure 5),
(Note 9)
Full
-
-
3000 ns
Driver Disable from Output High
Driver Disable from Output Low
Driver Enable from Shutdown to
Output High
tHZ
tLZ
tZH(SHDN)
RL = 1kΩ, CL = 50pF, SW = GND (Figure 5)
RL = 1kΩ, CL = 50pF, SW = VCC (Figure 5)
RL = 1kΩ, CL = 50pF, SW = GND (Figure 5),
(Notes 11, 12)
Full
-
Full
-
Full
-
-
250
ns
-
250
ns
-
3000 ns
Driver Enable from Shutdown to
Output Low
tZL(SHDN) RL = 1kΩ, CL = 50pF, SW = VCC (Figure 5),
(Notes 11, 12)
Full
-
-
3000 ns
Time to Shutdown
tSHDN (Note 11)
Full
50
500 1200 ns
Receiver Input to Output Delay
tPLH, tPHL (Figure 7)
Full
-
180 1000 ns
Receiver Skew | tPLH - tPHL |
tSKD (Figure 7)
Full
-
35
250
ns
Receiver Enable to Output High
tZH
RL = 1kΩ, CL = 15pF, SW = GND (Figure 8), (Note 10) Full
-
-
100
ns
Receiver Enable to Output Low
tZL
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8), (Note 10) Full
-
-
100
ns
Receiver Disable from Output High
tHZ
RL = 1kΩ, CL = 15pF, SW = GND (Figure 8)
Full
-
-
75
ns
Receiver Disable from Output Low
tLZ
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8)
Full
-
-
75
ns
Receiver Enable from Shutdown to tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 8),
Output High
(Notes 11, 13)
Full
-
-
5500 ns
Receiver Enable from Shutdown to tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8),
Output Low
(Notes 11, 13)
Full
-
-
5500 ns
9
FN7967.0
June 22, 2012