HSP50214B_14 Datasheet, PDF (9/62 Pages) Intersil Corporation – Programmable Downconverter

HSP50214B
14-Bit Input and Processing Resolution
The PDC maintains a minimum of 14-bits of processing
resolution through to the output, providing over 84dB of
dynamic range. The 18-bits of resolution on the internal
references provide a spurious floor that is better than 98dBc.
Furthermore, the PDC provides up to 42dB of gain scaling to
compensate for any change in gain in the RF front end as
well as up to 96dB of gain in the internal PDC AGC. This
gain maximizes the output resolution for small signals and
compensates for changes in the RF front end gain, to handle
changes in the incoming signal.
Summary
The greatest feature of the PDC is its ability to be
reconfigured to process many common standards in the
communications industry. Thus, a single hardware element
can receive and process a wide variety of signals from PCS
to traditional cellular, from wireless local loop to SATCOM.
The high resolution frequency tuning and narrowband
filtering are instrumental in almost all of the applications.
Multiple Chip Synchronization
Multiple PDCs are synchronized using a MASTER/SLAVE
configuration. One part is responsible for synchronizing the
front end internal circuitry using CLKIN while another part is
responsible for synchronizing the backend internal circuitry
using PROCCLK.
The PDC is synchronized with other PDCs using five control
lines: SYNCOUT, SYNCIN1, SYNCIN2, MSYNCO, and
MSYNCI. Figure 2 shows the interconnection of these five
signals for multiple chip synchronization where different
sources are used for CLKIN and PROCCLK.
PDC A is the Master sync through MSO.
PDC B configures the CLKIN sync through SYNCIN1.
PDC A configures the PROCCLK sync through SYNCIN2.
A
B
HSP50214B
MSYNCO
HSP50214B
MSYNCO
MSYNCI
(MASTER
SYNCIN2) ^SYNCOUT
SYNCIN2
MSYNCI
(MASTER
SYNCOUT _SYNCIN1)
SYNCIN2
SYNCIN1
SYNCIN1
ALL OTHER SYNCIN1
ALL OTHER SYNCIN2
ALL OTHER MSI
FIGURE 2. SYNCHRONIZATION CIRCUIT
SYNCOUT for PDC B should be set to be synchronous with
CLKIN (Control Word 0, Bit 3 = 0. See the Microprocessor
Write Section). SYNCOUT for PDC B is tied to the SYNCIN1
of all the PDCs. The SYNCIN1 can be programmed so that
the carrier NCO and/or the 5th order CIC filter of all PDCs can
be synchronously loaded/updated using SYNCIN1. See
Control Word 0, Bits 19 and 20 in the Microprocessor Write
Section for details.
SYNCOUT for one of the PDC’s other than PDC B, should
be set for PROCCLK (bit 3 = 1 in Control Word 0). This
output signal is tied to the SYNCIN2 of all PDCs. The
SYNCIN2 can be programmed so that the AGC updates its
accumulator with the contents in the master registers
(Control Word 8, Bit 29 in the Microprocessor Write Section).
SYNCIN2 is also used to load or reset the timing NCO using
bit 5, Control Word 11. The halfband and FIR filters can be
reset on SYNCIN2 using Control Word 7, Bit 21. The
MSYNCO of one of the PDCs is then used to drive the
MSYNCI of all the PDCs (including its own).
For application configurations where CLKIN and PROCCLK
have the same source, SYNCIN1 and SYNCIN2 can be tied
together. However, if different enabling is desired for the
front end and backend processing of the PDC’s, these
signals can still be controlled independently.
In the HSP50214B, the Control Word 25 reset signal has
been extended so that the front end reset is 10 CLKIN
periods wide and the back end reset is 10 PROCCLK
periods wide. This guarantees that no enables will be caught
in the pipelines. In addition, the SYNCIN1 internal reset
signal, which is enabled by setting Control Word 7,
Bit 21 = 1, has been extended to 10 cycles.
In summary, SYNCIN1 is used to update carrier phase
offset, update carrier center frequency, reset CIC decimation
counters and reset the carrier NCO (clear the feedback in
the NCO). SYNCIN2 is used to reset the HB filter, FIR filter,
re-sampler / HB state machines and the output FIFO, load a
new gain into the AGC and load a new re-sampler NCO
center frequency and phase offset.
Input Section
The block diagram of the input controller is provided in
Figure 3. The input can support offset binary or two’s
complement data and can be operated in gated or
interpolated mode (see Control Word 0 from the
Microprocessor Write Section). The gated mode takes one
sample per clock when the input enable (ENI) is asserted.
The gated mode allows the user to synchronize a low speed
sampling clock to a high speed CLKIN.
The interpolated mode allows the user to input data at a low
sample rate and to zero-stuff the data prior to filtering. This
zero stuffing effectively interpolates the input signal up to the
rate of the input clock (CLKIN). This interpolated mode
allows the part to be used at rates where the sampling
frequency is above the maximum input rate range of the
halfband filter section, and where the desired output
bandwidth is too wide to use a Cascaded Integrator Comb
(CIC) filter without significantly reducing the dynamic range.
9
FN4450.4
May 1, 2007