HSP50214B_14 Datasheet, PDF (35/62 Pages) Intersil Corporation – Programmable Downconverter

HSP50214B
SEROUTB:
end >
CONTROL WORD 19 FIELD
I (15:0)
(2’s COMP)
AGC DATA SERIAL OUTPUT TAG BIT †
TIMING ERROR DATA SERIAL OUTPUT TAG BIT †
FREQUENCY DATA SERIAL OUTPUT TAG BIT †
PHASE DATA SERIAL OUTPUT TAG BIT †
MAGNITUDE DATA SERIAL OUTPUT TAG BIT †
Q DATA SERIAL OUTPUT TAG BIT †
I DATA SERIAL OUTPUT TAG BIT †
DATA SOURCE FOR SEROUTA †
LINK FOLLOWING I DATA †
LINK FOLLOWING Q DATA †
LINK FOLLOWING MAG DATA †
LINK FOLLOWING PHASE DATA †
LINK FOLLOWING FREQ DATA †
LINK FOLLOWING TIMING DATA †
LINK FOLLOWING AGC DATA †
SHIFT REG
FOLLOWS I
SHIFT REG
XXX
000
001
010
011
100
101
110
111
SOURCE
I
Q
MAG
PHASE
FREQUENCY
TIMING ERROR
AGC
ZERO
Q (15:0)
(2’s COMP)
SHIFT REG
FOLLOWS Q
SHIFT REG
|r| (15:0)
(O; UNSIGNED BINARY)
φ (15:0)
(2’s COMP)
SHIFT REG
SHIFT REG
f (15:0)
(2’s COMP)
SHIFT REG
TE
(15:0)
(2’s COMP)
AGC
(15:0)
(O; UNSIGNED BINARY)
ZERO
SHIFT REG
SHIFT REG
SHIFT REG
MUX
SEROUTB
SOURCE
PROCCLK
PROGRAMMABLE
DIVIDER
NUM OF SER WORD LINKS IN A CHAIN †
SERIAL OUT CLOCK DIVIDER †
SERIAL OUTPUT SYNC POSITION †
SERIAL OUTPUT CLOCK POLARITY †
SERIAL OUTPUT SYNC POLARITY †
CROSS
MATRIX
SWITCH
CROSS
MATRIX
SWITCH
FOLLOWS |r|
SHIFT REG
FOLLOWS φ
SHIFT REG
FOLLOWS f
SHIFT REG
FOLLOWS TE
SHIFT REG
FOLLOWS AGC
SHIFT REG
SEROUTA
SOURCE
DATA SOURCE FOR SEROUTB †
6
5
4
3
2
1
0
SERIAL OUTPUT SHIFT REGISTER
SEROUTA
6
5
4
3
2
1
0
SERIAL OUTPUT SHIFT REGISTER
SEROUTB
‡
SERCLK
‡
SERSYNC
† Controlled via microprocessor interface
‡ Polarity is programmable
FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM
35
FN4450.4
May 1, 2007