HSP50214B_14 Datasheet, PDF (52/62 Pages) Intersil Corporation – Programmable Downconverter

HSP50214B
CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-17 Reserved
Reserved.
16-15 Phase Multiplier
These bits program allow the phase output of the cartesian to polar converter to be multiplied by 1, 2, 4, or
8 (modulo 2π) to remove phase modulation before the frequency is measured.
00- No Shift on Phase Input to frequency discriminator.
01- Shift Phase Input to frequency discriminator up 1 (one bit), discarding the MSB and zero filling the LSB.
10- Shift Phase Input to frequency discriminator up 2 (two) bits, discarding the MSB and zero filling the LSB.
11- Shift Phase Input to frequency discriminator up 3 (three) bits, discarding the MSB and zero filling the LSB.
14
Discriminator Enable 0- Disable Discriminator.
1- Enable Discriminator.
13-11
Discriminator FIR
Decimation
The decimation can be programmed from 1 to 8, where 000 = decimate by 8; 001 = decimate by 1; 010 =
decimate by 2; 011 = decimate by 3; 100 = decimate by 4; 101 = decimate by 5; 110 = decimate by 6; and
111 - decimate by 7.
10
FIR Symmetry Type 0- Odd Symmetry.
1- Even Symmetry.
9
FIR Symmetry
0- Symmetric.
1- Asymmetric.
8-3
Number of FIR Taps Number of FIR taps from 1 to 63, where 00000 is not valid (00001 = 1 tap, 00010 = 2 taps, etc. up to 11111
= 63 taps). Bit 8 is the MSB.
2-0
Discriminator Delay Sets the number of delays from 1 to 8 in the discriminator. Set delay ddd to delay minus 1, where 000
represents 1 delay; 001 represents 2 delays, 010 represents 3 delays, 011 represents 4 delays, 100
represents 5 delays, 101 represents 6 delays, 110 represents 7 delays, and 111 represents 8 delays. If ddd
the decimal representation bits 2-0, then the discriminator a transfer function H(Z) = 1-Z^{-(ddd + 1)}.
BIT
POSITION
31-28
27-16
11-0
CONTROL WORD 18: TIMING ERROR PRELOADS (SYNCHRONIZED TO PROCCLK)
FUNCTION
Reserved
NCO Divide
Reference Divide
DESCRIPTION
Reserved.
The Re-Sampler NCO output is divided down by the value loaded into this register plus 1. Load with a
value that is one less than the desired period. Bit 27 is the MSB.
The reference clock is divided down by the value loaded into this register plus 1. Load with a value that
is one less than the desired period. Bit 27 is the MSB. A minimum preload of “I” is required.
BIT
POSITION
31
30-28
27-25
24-21
20-18
CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK)
FUNCTION
DESCRIPTION
Reserved
Reserved.
Data Source for
SEROUTA
Serial Output A Source. The serial data source is selected using Table 12 (see Output Section).
Data Source for
SEROUTB
Serial Output B Source. The serial data source is selected using Table 12 (see Output Section).
Number of Serial Word
Links in a Chain
This parameter determines the number of SERSYNC pulses generated. It can be set from 1 to 7. If this
parameter matches the number of serial words that are linked together to form a serial output chain, then
there will be a sync pulse for every word in the serial output. In applications where a processor is
receiving the serial data, it may be desirable to have a single SERSYNC pulse for the whole serial output
chain, instead of a SERSYNC for each word in the data chain. The processor then parses out the various
data words. As an example, if the I and Q are chained together and a single SERSYNC pulse is
generated for this serial output chain, no ambiguity exists in the processor about which two data samples
(one from I and one from Q) are related.
Link Following I Data The serial data word, or link, following the I data word is selected using Table 12
(see Output Section).
52
FN4450.4
May 1, 2007