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HD-6409_05 Datasheet, PDF (9/12 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder
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HD-6409
Capacitance TA = +25°C, Frequency = 1MHz
SYMBOL
PARAMETER
CIN
COUT
Input Capacitance
Output Capacitance
TYP
UNITS
TEST CONDITIONS
10
pF
All measurements are referenced to device GND
12
pF
AC Electrical Specifications VCC = 5.0V ±10%, TA = -40°C to +85°C (HD-6409-9)
SYMBOL
PARAMETER
MIN
MAX
UNITS
(NOTE 1) TEST CONDITIONS
fC
Clock Frequency
-
16
MHz
-
tC
Clock Period
1/fC
-
sec
-
t1
Bipolar Pulse Width
tC+10
-
ns
-
t3
One-Zero Overlap
-
tC-10
ns
-
tCH
Clock High Time
20
-
ns
f = 16.0MHz
tCL
Clock Low Time
20
-
ns
f = 16.0MHz
tCE1
Serial Data Setup Time
120
-
ns
-
tCE2
Serial Data Hold Time
0
-
ns
-
tCD2
DCLK to SDO, NVM
-
40
ns
-
tR2
ECLK to BZO
-
40
ns
-
tr
Output Rise Time (All except Clock)
-
50
ns
From 1.0V to 3.5V, CL = 50pF, Note 2
tf
Output Fall Time (All except Clock)
-
50
ns
From 3.5V to 1.0V, CL = 50pF, Note 2
tr
Clock Output Rise Time
-
11
ns
From 1.0V to 3.5V, CL = 20pF, Note 2
tf
Clock Output Fall Time
-
11
ns
From 3.5V to 1.0V, CL = 20pF, Note 2
tCE3
ECLK to BZO, BOO
0.5
1.0
DBP Notes 2, 3
tCE4
CTS Low to BZO, BOO Enabled
0.5
1.5
DBP Notes 2, 3
tCE5
CTS Low to ECLK Enabled
10.5
11.5
DBP Notes 2, 3
tCE6
CTS High to ECLK Disabled
-
1.0
DBP Notes 2, 3
tCE7
CTS High to BZO, BOO Disabled
1.5
2.5
DBP Notes 2, 3
tCD1
UDI to SDO, NVM
2.5
3.0
DBP Notes 2, 3
tCD3
RST Low to CDLK, SDO, NVM Low
0.5
1.5
DBP Notes 2, 3
tCD4
RST High to DCLK, Enabled
0.5
1.5
DBP Notes 2, 3
tR1
UDI to BZO, BOO
0.5
1.0
DBP Notes 2, 3
tR3
UDI to SDO, NVM
2.5
3.0
DBP Notes 2, 3
NOTES:
1. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH ≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and 5.5V.
Input rise and fall times driven at 1ns/V, Output load = 50pF.
2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested.
3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.
9
FN2951.2
July 29, 2005
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