 English |
|
|
|
|
|
|
|
| HD-6409_05 Datasheet, PDF (12/12 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder | |||
| |||
| ◁ |
Timing Waveforms (Continued)
HD-6409
UDI
ECLK
BZO
SDO
NVM
MANCHESTER â1â
MANCHESTER â0â
MANCHESTER â0â
MANCHESTER â1â
tR2
tR2
tR1
MANCHESTER â1â
tR3
MANCHESTER â0â
MANCHESTER â0â
tR3
FIGURE 17. REPEATER TIMING
Test Load Circuit
DUT
CL
(NOTE)
NOTE: INCLUDES STRAY AND JIG
CAPACITANCE
FIGURE 18. TEST LOAD CIRCUIT
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporationâs quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN2951.2
July 29, 2005
|
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese