CD4066BMS Datasheet, PDF (9/9 Pages) Intersil Corporation – CMOS 4-Bit Magnitude Comparator

CD4066BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T_A) = +25^oC
3 VDD = 2.5V, VSS = -2.5V
INPUT = TERM 1, OUTPUT = TERM 2
10K
2
RL = 100K
1K
500Ω
1
100Ω
0 _100Ω
VC = VDD VDD
-1 _500Ω
VIS CD4066BMS VOS
1 OF 4
SWITCHES
-2 ^1K
RL
10K
ALL UNUSED TERMINALS ^VSS
-3 ^{100K ARE CONNECTED TO VSS}
-3 -2 -1
0
1
2
3
4
INPUT VOLTAGE (VI) (V)
FIGURE 16. TYPICAL ON CHARACTERISTICS FOR 1 OF 4
CHANNELS
10⁴
8
6
4
2
AMBIENT TEMPERATURE (T_A) = +25^oC
SUPPLY VOLTAGE (VDD) = 15V
10³ ₈
6
4
2
10²
8
6
10V
5V
f
VDD
14
5
6 _CD4066/
12
BMS
4
13
2
7
10
2
10
4 68
2
4
10²
SWITCHING FREQUENCY (f) (kHz)
VSS
68
10³
FIGURE 17. POWER DISSIPATION PER PACKAGE vs
SWITCHING FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10^-3 inch).
Special Considerations
In applications that employ separate power sources to drive
VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the
four CD4066B bilateral switches). This provision avoids any
permanent current flow or clamp action on the VDD supply
when power is applied or removed from the CD4066B.
In certain applications, the external load-resistor current may
include both VDD and signal line components. To avoid
drawing VDD current when switch current flows into termi-
nals 1, 4, 8 or 11 the voltage drop across the bidirectional
switch must not exceed 0.8 volts (calculated from RON val-
ues shown).
No VDD current will flow through RL if the switch current
flows into terminals 2, 3, 9, or 10.
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-974