CD4066BMS Datasheet, PDF (7/9 Pages) Intersil Corporation – CMOS 4-Bit Magnitude Comparator

CD4066BMS
REP
VC
RATE
tr = tf = 20ns
VOS ^90%
20ns
1
10%
0
20ns
VC = VDD
VDD
tr = tf = 20ns
VDD
VDD
CD4066BMS
1 OF 4 SWITCHES
VSS
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VOS
50
pF
1kΩ
+10V
ALL UNUSED INPUTS
VC
VDD = +10V ARE CONNECTED TO VSS
tr = tf = 20ns
VIS = +10V
CD4066BMS
1 OF 4 SWITCHES
VSS
VOS = ¹/₂VOS
AT 1kHz
50
pF
1kΩ
FIGURE 8. PROPAGATION DELAY TPLH, TPHL CONTROL
SIGNAL OUTPUT. DELAY IS MEASURED AT VOS
LEVEL OF +10% FROM GROUND (TURN ON) OR
ON-STATE OUTPUT LEVEL (TURN OFF).
FIGURE 9. MAXIMUM ALLOWABLE CONTROL INPUT REPETI-
TION RATE
CLOCK ₁₄
RESET ₁₅
1
10 2 3 7 9 12
PE J1 J2 J3 J4 J5
CD4018B
Q1 Q2
54
13
1 ¹/₄ CD4066B 2
CLOCK ₁₄
EXT
RESET
15
1
10 2 3 7 9 12
PE J1 J2 J3 J4 J5
CD4018B
Q1 Q2
54
3
2
1_{/3 CD4049B}
5
4
1
3
2
5
4
6
CD4001B
8
10
9
7
6
1_{/3 CD4049B}
9
10
13 12 9 8 6 5 2 1
CD4001B
11
10
4
3
SIGNALS
INPUTS
12
13
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
PACKAGE COUNT
2 - CD4001B
1 - CD4049B
3 - CD4066BMS
2 - CD4018B
6 5 13
11
12
1
2
4 ^{CD4066B 3}
8
9
11
10
10K
CLOCK
12 6 5 11
11
12
1_{/6 CD4049B}
5
4 1_{/4 CD4066B}
VDD
2
10K
1
4
38
11
3
10K
CD4066B
9
10K
MAX. ALLOWABLE
30% (VDD - VSS)
10
SIGNAL LEVEL
VSS
CHAN. 1 CHAN. 2 CHAN. 3 CHAN. 4
10K
SIGNALS
OUTPUTS
LPF ^{CHANNEL 1}
LPF ^{CHANNEL 2}
LPF ^{CHANNEL 3}
LPF ^{CHANNEL 4}
FIGURE 10. 4 CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM
7-972