CD4066BMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS 4-Bit Magnitude Comparator

Schematic
CONTROL
CONTROL
VC
*
PN
N
VSS
CD4066BMS
SWITCH
IN
VIS
P
OUT
N
VOS
SIGNAL LEVEL RANGE:
VSS ≤ VIS ≤ VDD
NORMAL OPERATION CONTROL
LINE BIASING:
SWITCH ON, VC “I” = VDD
SWITCH OFF, VC “O” = VSS
* ^{ALL CONTROL INPUTS ARE}
PROTECTED BY THE CMOS
PROTECTION NETWORK
NOTE:
All “P” Substrates
Connected to VDD
VDD
VSS
FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 4 IDENTICAL SWITCHES AND ITS ASSOCIATED CONTROL CIRCUITRY
IIS
VIS
CD4066BMS
1 OF 4 SWITCHES
|VIS - VOS|
RON =
|IIS|
VOS
VDD
10kΩ
VSS
KEITHLY 160 DIGITAL
MULTIMETER
TG
“ON”
1kΩ
RANGE ^Y
X
X-Y
PLOT TER
HP
MOSELEY
7030A
FIGURE 2. DETERMINATION OF RON AS A TEST CONDITION
FOR CONTROL INPUT HIGH VOLTAGE (VIHC)
SPECIFICATION
FIGURE 3. CHANNEL ON-STATE RESISTANCE MEASURE-
MENT CIRCUIT
CIOS
VC = -5V
VDD = +5V
CD4066BMS
1 OF 4 SWITCHES
MEASURED ON BOONTON
CAPACITANCE BRIDGE
MODEL 75A (1MHz)
TEST FIXTURE CAPACITANCE
NULLED OUT
CIS
COS
VSS = -5V
FIGURE 4. CAPACITANCE TEST CIRCUIT
VC = VSS
VDD
VIS = VDD
CD4066BMS
1 OF 4 SWITCHES
Ι
VSS
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
FIGURE 5. OFF SWITCH INPUT OR OUTPUT LEAKAGE
VC = VDD
VDD
ViS
CD4066BMS
1 OF 4 SWITCHES
VDD
VSS
tr = tf = 20ns
ALL UNUSED INPUTS
ARE CONNECTED TO VSS
VOS
50
pF
200kΩ
+10V
VC
tr = tf = 20ns
VDD
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VIS
CD4066BMS
VOS
1 OF 4 SWITCHES
1kΩ
VSS
10kΩ
FIGURE 6. PROPAGATION DELAY TIME SIGNAL INPUT (VIS) FIGURE 7. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT
TO SIGNAL OUTPUT (VOS)
7-971