CD4029BMS Datasheet, PDF (9/11 Pages) Intersil Corporation – CMOS Presettable Up/Down Counter

CD4029BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T_A) = +25^oC
300
SUPPLY VOLTAGE (VDD) = 5V
200
10V
100
15V
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (CARRY
OUTPUT)
10^{5 8}
6
4
SUPPLY VOLTAGE (VDD) = 15V
2
10⁴ 8
6
10V
4
2
10³ 8
6
10V
5V
4
2
10² 8
6
4
2
10
2
1
4 68 2
10
CL = 50pF
CL = 15pF
AMBIENT TEMPERATURE (T_A) = +25^oC
4 68 2 4 68 2 4 68 2 4 68
10²
10³
10⁴
CLOCKFREQUENCY (fCL) (kHz)
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION
OF FREQUENCY
Timing Diagrams
CLOCK (CL)
CARRY IN
(CL ENABLE)
UP/DOWN
BINARY/
DECADE
PRESET
ENABLE
J1
J2
J3
J4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT 5 6 7 8 9 10 11 12 13 14 15 9 8 7 6 5 4 3 2 1 0 0 15
The CD4029BMS CLOCK and UP/DOWN inputs are used
directly in most applications. In applications where CLOCK
UP and CLOCK DOWN inputs are provided, conversion to
the CD4029BMS CLOCK and UP/DOWN inputs can easily
be realized by use of the circuit in Figure 11.
CD4029BMS changes count on positive transitions of
CLOCK UP or CLOCK DOWN inputs. For the gate configu-
ration in Figure 12, when counting up the CLOCK DOWN
input must be maintained high and conversely when count-
ing down the CLOCK UP input must be maintained high.
“CLOCK UP”
“CLOCK
DOWN”
VDD
“UP/DOWN”
“CLOCK”
1 CD4011
QUAD 2 INPUT NAND GATE
FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN
INPUT SIGNALS TO CLOCK AND UP/DOWN
INPUT SIGNALS
7-806