CD4029BMS Datasheet, PDF (10/11 Pages) Intersil Corporation – CMOS Presettable Up/Down Counter

CD4029BMS
Timing Diagrams (Continued)
CLOCK (CL)
CARRY IN
(CL ENABLE)
UP/DOWN
BINARY/
DECADE
PRESET
ENABLE
J1
J2
J3
J4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT
01 2 34567898 76543210098 7
UP/DOWN
PRESET
ENABLE
FIGURE 12. TIMING DIAGRAM-DECADE MODE
“PARALLEL CLOCKING”
UP/D PE J1 J2 J3 J4
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
*
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
CLOCK
BINARY/
DECADE
*CARRY OUT LINES AT THE 2ND, 3RD, ETC, STAGES MAY HAVE A NEG-
ATIVE-GOING GLITCH PULSE RESULTING FROM DIFFERENTIAL
DELAYS OF DIFFERENT CD4029BMS IC’S. THESE NEGATIVE GOING
GLITCHES DO NOT AFFECT PROPER CD4029BMS OPERATION. HOW-
EVER, IF THE CARRY OUT SIGNALS ARE USED TO TRIGGER OTHER
EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF’S OR COUNTERS, THE
CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL
USING A 2-INPUT OR GATE SUCH AS CD4071BMS.
FIGURE 13. CASCADING COUNTER PACKAGES
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
807