CD4018BMS Datasheet, PDF (9/9 Pages) Intersil Corporation – CMOS Presettable Divide-By- “N” Counter

CD4018BMS
EXTERNAL CONNECTIONS FOR DIVIDE BY 10, 9, 8, 7, 6, 5, 4, 3,
OPERATION
DIVIDE BY 10 Q5 Connected
No External Components
Back To “Data” Required
DIVIDE BY 8 Q4 Connected
No External Components
Back To “Data” Required
DIVIDE BY 6 Q3 Connected
No External Components
Back To “Data” Required
DIVIDE BY 4 Q2 Connected
No External Components
Back To “Data” Required
DIVIDE BY 2 Q1
DIVIDE BY 9
1/2 CD4011B
Q4
Q5
CONNECTED BACK TO “DATA”
(SKIPS “ALL-I’s” STATE)
J1 J2 J3 J4 J5
CL
D
R
Q3 Q4
CL ÷ 7
FIGURE 13. EXAMPLE OF DIVIDE BY 7
Chip Dimensions and Pad Layout
DIVIDE BY 7
1/2 CD4011B
Q3
Q4
CONNECTED BACK TO “DATA”
(SKIPS “ALL-I’s” STATE)
DIVIDE BY 5
1/2 CD4011B
Q2
Q3
CONNECTED BACK TO “DATA”
(SKIPS “ALL-I’s” STATE)
DIVIDE BY 3
1/2 CD4011B
Q1
Q2
CONNECTED BACK TO “DATA”
(SKIPS “ALL-I’s” STATE)
FIGURE 12. EXTERNAL CONNECTIONS FOR DIVIDE BY 10, 9,
8, 7, 6, 5, 4, 3, 2 OPERATION
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10^-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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