CD4018BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Presettable Divide-By- “N” Counter

CD4018BMS
November 1994
CMOS Presettable
Divide-By- “N” Counter
Features
Description
• High Voltage Type (20V Rating)
• Medium Speed Operation 10MHz (typ.) at VDD - VSS =
10V
• Fully Static Operation
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25^oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Fixed and Programmable Divided- By-10, 9, 8, 7, 6, 5,
4, 3, 2 Counters
• Fixed and Programmable Counters Greater Than 10
• Programmable Decade Counters
• Divide-By- “N” Counters/Frequency Synthesizers
• Frequency Division
• Counter Control/Timers
CD4018BMS types consist of 5 Johnson-Counter stages,
buffered Q outputs from each stage, and counter preset con-
trol gating. CLOCK, RESET, DATA, PRESET ENABLE, and
5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or
2 counter configurations can be implemented by feeding the
Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA
input. Divide-by-9, 7, 5, or 3 counter configurations can be
implemented by the use of a CD4011B to gate the feedback
connection to the DATA input. Divide-by functions greater
than 10 can be achieved by use of multiple CD4018BMS
units. The counter is advanced one count at the positive
clock-signal transition. Schmitt Trigger action on the clock
line permits unlimited clock rise and fall times. A high
RESET signal clears the counter to an all-zero condition. A
high PRESET-ENABLE signal allows information on the JAM
inputs to preset the counter. Anti-lock gating is provided to
assure the proper counting sequence.
The CD4018BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
Functional Diagram
JAM INPUTS VDD
“2”
“4”
“1” “3” “5”
2 3 7 9 12 16
Pinout
CD4018BMS
TOP VIEW
DATA 1
JAM 1 2
JAM 2 3
Q2 4
Q1 5
Q3 6
JAM 3 7
VSS 8
16 VDD
15 RESET
14 CLOCK
13 Q5
12 JAM 5
11 Q4
10 PRESET ENABLE
9 JAM 4
PRESET ¹⁰
ENABLE
CLOCK ¹⁴
DATA
1
RESET ¹⁵
5
Q1
4
Q2
6 _Q3
11 _Q4
13 _Q5
8
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-350
File Number 3298