CD40100BMS Datasheet, PDF (9/9 Pages) Intersil Corporation – CMOS 32-Stage Static Left/Right Shift Register

CD40100BMS
Typical Performance Characteristics (Continued)
8
6
4
SUPPLY VOLTAGE (VDD) = 15V
2
10⁵
8
6
4
CL = 50pF
CL =15pF
2
10⁴
8
6
4
10V
10V
2
10³
8
5V
6
4
2
10²
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
1
10
10²
10³
10⁴
CLOCK INPUT FREQUENCY (fCL) (KHz)
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
Timing Diagram
CLOCK
INPUT
tWL
tWH
tS
tH
tPHL
OUTPUT
tPHL
FIGURE 9. TIMING DIAGRAM DEFINING SETUP, HOLD, AND PROPAGATION DELAY TIMES
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in mils
(10^-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1285