CD40100BMS Datasheet, PDF (7/9 Pages) Intersil Corporation – CMOS 32-Stage Static Left/Right Shift Register

Logic Diagram
CD40100BMS
CLOCK
3*
CLOCK INHIBIT
2*
SHIFT RIGHT
11*
INPUT
LEFT/RIGHT
13*
CONTROL
RECIRCULATE
9*
CONTROL
R
p
n
R
p
n
R
S
S
R
R
VDD
VSS
* ^{ALL INPUTS ARE PROTECTED}
BY CMOS PROTECTION
CL
NETWORK
p
n
CL
SHIFT LEFT
6*
INPUT
CL
CL
S
p
n
S
S
CL CL
p
STAGE 1
n
S
S
CL CL
p
STAGE 2
n
S
STAGES 3-30
(ALL IDENTICAL TO
STAGES 2 AND 31)
S
CL CL
p
STAGE 31
n
S
CL
CL CL
p
STAGE 32
n
CL
CL
p
S
n
p
CL
n
S
S
p
n
S
SHIFT RIGHT
12
OUTPUT
CL
p
n
CL
S
p
n
S
S
R
p
p
n
n
R
S
p
n
R
SHIFT RIGHT
12
OUTPUT
CL
p
D
n
CL
CL
p
n
CL
CL
p
n
Q
CL
CL
p
n
CL
FIGURE 1.
7-1283