CD40100BMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS 32-Stage Static Left/Right Shift Register

Specifications CD40100BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
INITIAL STATE
TABLE 9. DATA TRANSFER TABLE*
CLOCK
DATA INPUT
CLOCK INHIBIT INTERNAL STAGE
0
0
X
X
0
0
1
0
X
X
0
1
X
1
1
0 = Low Level 1 = High Level X = Don’t Care NC = No Change
* For Shift-Right Mode
Data Input = SHIFT RIGHT INPUT (Term. 11)
Internal Stage = Stage 1 (Q1)
Output = SHIFT LEFT OUTPUT (Term. 4)
For Shift Left Mode
Data Input = SHIFT LEFT INPUT (Term. 6)
Internal Stage = Stage 32 (Q32)
Output = SHIFT RIGHT OUTPUT (Term. 12)
LEVEL CHANGE
X
RESULTING STATE
INTERNAL
STAGE Q
OUTPUT
0
NC
NC
0
1
NC
NC
1
NC
NC
LEFT/RIGHT
CONTROL
1
1
0
0
X
TABLE 10. CONTROL TRUTH TABLE
CLOCK INHIBIT
RECIRCULATE
CONTROL
ACTION
0
1
Shift Left
0
0
Shift Left
0
1
Shift Right
0
0
Shift Right
1
X
No Shift
INPUT BIT ORIGIN
Shift Left Input
Stage 1
Shift Right Input
Stage 32
-
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