X9409_15 Datasheet, PDF (8/19 Pages) Intersil Corporation – Low Noise/Low Power/2-Wire Bus Quad Digita Controlled Potentiometers

TIMING DIAGRAMS
START and STOP Timing
(START)
SCL
t_SU:STA
SDA
X9409
t_R
t_HD:STA
t_R
t_F
t_SU:STO
t_F
(STOP)
Input Timing
t_CYC
SCL
SDA
t_SU:DAT
t_HIGH
t_LOW
t_HD:DAT
t_BUF
Output Timing
SCL
SDA
t_AA
Power-up Requirements
(Power-up sequencing can affect correct recall of the wiper
registers)
The preferred power-on sequence is as follows: First V_CC, then
the potentiometer pins, R_H, R_L and R_W. The V_CC ramp rate
specification should be met and any glitches or slope changes in
the V_CC line should be held to <100mV if possible. If V_CC powers
down, it should be held below 0.1V for more than 1 second
before powering up again in order for proper wiper register recall.
Also, V_CC should not reverse polarity by more than 0.5V. Recall of
wiper position will not be complete until V_CC reaches its final
value.
t_DH
Device Addressing
Following a start condition the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier (see Figure 4). For the
X9409 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
0
1
0
1 _{A3 A2 A1 A0}
DEVICE ADDRESS
FIGURE 4. SLAVE ADDRESS
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FN8192.6
September 3, 2015