X9409_15 Datasheet, PDF (3/19 Pages) Intersil Corporation – Low Noise/Low Power/2-Wire Bus Quad Digita Controlled Potentiometers

X9409
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the X9409.
SERIAL DATA (SDA)
The SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-O Red
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A₀, A₂, A₃)
The address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9409. A maximum of 16 devices may
occupy the 2-wire serial bus.
Potentiometer Pins
V_H0/R_H0 - V_H3/R_H3, V_L0/R_L0 - V_L3/R_L3
The V_H/R_H and V_L/R_L inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V_W0/R_{W0 -} V_W3/R_W3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and the
serial interface logic providing direct communication between the
host and the XDCP potentiometers.
Serial Interface
The X9409 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (t_LOW). The SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
START CONDITION
All commands to the X9409 are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH
(t_HIGH). The X9409 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command until
this condition is met.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is HIGH.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a positive
handshake between the master and slave devices on the bus to
indicate the successful receipt of data. The transmitting device,
either the master or the slave, will release the SDA bus after
transmitting eight bits. The master generates a ninth clock cycle
and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of data.
The X9409 will respond with an acknowledge after recognition of
a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9409 will respond with a final
acknowledge.
ARRAY DESCRIPTION
The X9409 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (V_H/R_H and V_L/R_L
inputs).
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (V_W/R_W) output. Within
each individual array only one switch may be turned on at a time.
These switches are controlled by the Wiper Counter Register
(WCR). The 6 bits of the WCR are decoded to select and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR can
be read and written by the host system.
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FN8192.6
September 3, 2015