X5168_06 Datasheet, PDF (8/20 Pages) Intersil Corporation – CPU Supervisor with 16Kbit SPI EEPROM

X5168, X5169
The Write Enable Latch (WEL) bit indicates the status of the
write enable latch. When WEL = 1, the latch is set HIGH and
when WEL = 0 the latch is reset LOW. The WEL bit is a
volatile, read only bit. It can be set by the WREN instruction
and can be reset by the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
STATUS
REGISTER BITS
BL1
BL0
0
0
0
1
1
0
1
1
ARRAY ADDRESSES PROTECTED
X5168/X5169
None
$0600-$07FF
$0400-$07FF
$0000-$07FF
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The flag bit is automatically reset upon
power-up.
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an in-circuit programmable ROM function (Table 2).
WP is LOW and WPEN bit programmed HIGH disables all
status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
In the locked state (programmable ROM mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s status register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile writes
to the status register operate normally. Setting the WPEN bit
in the status register to “0” blocks the WP pin function,
allowing writes to the status register when WP is HIGH or
LOW. Setting the WPEN bit to “1” while the WP pin is LOW
activates the programmable ROM mode, thus requiring a
change in the WP pin prior to subsequent status register
changes. This allows manufacturing to install the device in a
system with WP pin grounded and still be able to program
the status register. Manufacturing can then load
configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to be
protected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
Instruction
SI
16 Bit Address
15 14 13
3210
High Impedance
SO
Data Out
7 654321 0
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
8
FN8130.2
June 15, 2006