X5168_06 Datasheet, PDF (11/20 Pages) Intersil Corporation – CPU Supervisor with 16Kbit SPI EEPROM

X5168, X5169
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
Data Byte
7 6 5 43 2 1 0
SO
Symbol Table
High Impedance
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11
FN8130.2
June 15, 2006