ISL6752 Datasheet, PDF (8/16 Pages) Intersil Corporation – ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control

ISL6752
Typical Performance Curves (Continued)
1-10⁴
CT = 680pF
1-10³
CT = 1000pF
CT = 220pF
100
CT = 330pF
CT = 100pF
CT = 470pF
10 ₀
10 20 30 40 50 60 70 80 90 100
RTD (kΩ)
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
1-10³
RTD = 10kΩ
100
RTD = 50kΩ
RTD = 100kΩ
100.1
1
10
CT (nF)
FIGURE 4. CAPACITANCE vs FREQUENCY
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF - The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200µA
current source and discharged with a user adjustable current
source controlled by RTD.
RTD - This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2V.
CS - This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1V nominal. The
CS pin is shorted to GND at the termination of either PWM
output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
OUTUL and OUTUR - These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0V to 2V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
OUTLL and OUTLR - These outputs control the lower bridge
FETs, are pulse width modulated, and operate in alternate
sequence. OUTLL controls the lower left FET and OUTLR
controls the lower right FET. The left and right designation
may be switched as long as they are switched in conjunction
with the upper FET outputs, OUTUL and OUTUR.
OUTLLN and OUTLRN - These outputs are the
complements of the PWM (lower) bridge FETs. OUTLLN is
the complement of OUTLL and OUTLRN is the complement
of OUTLR. These outputs are suitable for control of
synchronous rectifiers. The phase relationship between
each output and its complement is controlled by the voltage
applied to VADJ.
VADJ - A 0V to 5V control voltage applied to this input sets
the relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR
and OUTLLN/OUTLRN.
8
FN9181.3
October 31, 2008