ISL6752 Datasheet, PDF (14/16 Pages) Intersil Corporation – ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control

ISL6752
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow, as indicated in Figure 13.
VIN+
UL
UR
D1
LL
VOUT+
LL
LR
D2
RTN
VIN-
FIGURE 13. UR - LL POWER TRANSFER CYCLE
The UR - LL power transfer period terminates when switch
LL turns off, as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance, which charges the
node to VIN and then forward biases the body diode of
upper switch UL. As before, the output inductor current
assists in this transition. The primary leakage inductance,
L_L, maintains the current, which now circulates around the
path of switch UR, the transformer primary, and switch UL.
When switch LL opens, the output inductor current free
wheels predominantly through diode D1. Diode D2 may
actually conduct very little or none of the free-wheeling
current, depending on circuit parasitics. This condition
persists through the remainder of the half-cycle.
VIN+
UL
IP
UR
LL
IS
D1
VOUT+
LL
LR
D2
RTN
VIN-
FIGURE 14. UR - UL FREE-WHEELING PERIOD
When the upper switches toggle, the primary current that was
flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward-biased. If RESDEL
is set properly, switch LR will be turned on at this time.
VIN+
UL
IP
UR
LL
IS
D1
VOUT+
LL
LR
D2
RTN
VIN-
FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 L_LI_P2),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Synchronous Rectifier Outputs and Control
The ISL6752 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 16. BASIC WAVEFORM TIMING
Referring to Figure 16, the SRs alternate between being both
on during the free-wheeling portion of the cycle (OUTLL/LR
off), and one or the other being off when OUTLL or OUTLR is
on. If OUTLL is on, its corresponding SR must also be on,
indicating that OUTLRN is the correct SR control signal.
Likewise, if OUTLR is on, its corresponding SR must also be
on, indicating that OUTLLN is the correct SR control signal.
A useful feature of the ISL6752 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
LR) and their complements (OUTLLN, OUTLRN) by ±300ns.
This feature allows the designer to compensate for
differences in the propagation times between the PWM FETs
and the SR FETs. A voltage applied to VADJ controls the
phase relationship.
14
FN9181.3
October 31, 2008