ISL6615A Datasheet, PDF (8/12 Pages) Intersil Corporation – High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features

ISL6615A
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q • VCC
P _{Q g _Q1}
=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_-----²_-
V_GS1
•
F_SW
•
N_Q
1
P _{Q g _Q2}
=
Q_{-----G-----2----}•_-----P_----V_----C_-----C_-----²_-
V_GS2
•
F_SW
•
N_Q2
(EQ. 2)
I_DR
=
⎛
⎜
⎝
Q_{-----G-----1----}•_-----P_----V_-----C_----C_------•_----N_{-----Q-----1-}
V_GS1
+
Q_{-----G-----2----}•_-----P_-V---V_-G----C_S----2C_------•_----N_{-----Q----2--⎠⎟⎞}
• F_SW + I_Q
(EQ. 3)
where the gate charge (Q_G1 and Q_G2) is defined at a
particular gate to source voltage (V_GS1and V_GS2) in the
corresponding MOSFET datasheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are the number of upper and lower MOSFETs,
respectively; PVCC is the drive voltage for both upper
and lower FETs. The IQ*VCC product is the quiescent
power of the driver without capacitive load and is
typically 200mW at 300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among
the resistive components along the transition path. The
drive resistance dissipates a portion of the total gate
drive power losses, the rest will be dissipated by the
external gate resistors (R_G1 and R_G2) and the internal
gate resistors (R_GI1 and R_GI2) of MOSFETs. Figures 3
and 4 show the typical upper and lower gate drives
turn-on transition path. The power dissipation on the
driver can be roughly estimated, as shown in Equation 4.
P_DR = P_{DR_UP} + P_{DR_LOW} + I_Q • VCC
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
R^-----_L^---_O^-----₁^{R----+-L---O-}R^----1-_E^----_X^----_T^---₁^- _{⎠⎟⎞}
• ^P-----^Q----^g----^_--^Q-----¹-
2
(EQ. 4)
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
•
P_{-----Q----g----_--Q-----2-}
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
PVCC
BOOT
D
R_HI1
R_LO1
C_GD
G
R_G1 ^RGI1
C_GS
S
C_DS
Q1
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON
PATH
PVCC
R_HI2
R_LO2
D
C_GD
G
R_G2 ^RGI2
C_GS
S
C_DS
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON
PATH
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs)
can cause serious ringing, exceeding the absolute
maximum ratings of the devices. A good layout helps
reduce the ringing on the switching node (PHASE) and
significantly lower the stress applied to the output drives.
The following advice is meant to lead to an optimized
layout and performance:
• Keep decoupling loops (VCC-GND, PVCC-GND and
BOOT-PHASE) short and wide (at least 25 mils). Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane
with at least two vias.
• Minimize trace inductance, especially on low-
impedance lines. All power traces (UGATE, PHASE,
LGATE, GND, PVCC, VCC, GND) should be short and
wide (at least 25 mils). Try to place power traces on
a single layer, otherwise, two vias on interconnection
are preferred where possible. For no connection (NC)
pins on the QFN part, connect it to the adjacent net
(LGATE2/PHASE2) can reduce trace inductance.
• Shorten all gate drive loops (UGATE-PHASE and
LGATE-GND) and route them closely spaced.
• Minimize the inductance of the PHASE node. Ideally,
the source of the upper and the drain of the lower
MOSFET should be as close as thermally allowable.
• Minimize the current loop of the output and input
power trains. Short the source connection of the
lower MOSFET to ground as close to the transistor
pin as feasible. Input capacitors (especially ceramic
decoupling) should be placed as close to the drain of
upper and source of lower MOSFETs as possible.
• Avoid routing relatively high impedance nodes (such
as PWM and ENABLE lines) close to high dV/dt
UGATE and PHASE nodes.
In addition, for heat spreading, place copper underneath
the IC whether it has an exposed pad or not. The copper
area can be extended beyond the bottom area of the IC
and/or connected to buried power ground plane(s) with
8
FN6608.1
April 22, 2010