ISL6615A Datasheet, PDF (3/12 Pages) Intersil Corporation – High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features

ISL6615A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6615ACBZ
6615A CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6615ACRZ
615A
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6615AIBZ
6615A IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL6615AIRZ
15AI
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL6615AFRZ
15AF
-40 to +125
10 Ld 3x3 DFN
L10.3x3
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6615A. For more information on MSL please
see techbrief TB363.
Pin Configurations
ISL6615A
(8 LD SOIC)
TOP VIEW
ISL6615A
(10 LD 3x3 DFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 PVCC
6 VCC
5 LGATE
UGATE 1
BOOT 2
N/C 3
PWM 4
GND ⁵
GND
10 PHASE
9 PVCC
8 _N/C
7 VCC
6 LGATE
COMMAND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC
Functional Pin Descriptions
PACKAGE PIN
#
SOIC DFN
1
1
2
2
-
3, 8
3
4
4
5
5
6
6
7
7
9
8
10
9
11
PIN
SYMBOL
FUNCTION
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this
pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET.
See the Internal Bootstrap Device “TIMING DIAGRAM” on page 6 under Description for guidance in
choosing the capacitor value.
N/C No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during
operation, see the “TIMING DIAGRAM” on page 6 section under Description for further details. Connect
this pin to the PWM output of the controller.
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return
of the driver.
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin
to GND.
PVCC This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V.
Place a high quality low ESR ceramic capacitor from this pin to GND.
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin
provides a return path for the upper gate drive.
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
3
FN6608.1
April 22, 2010