ISL6235 Datasheet, PDF (8/14 Pages) Intersil Corporation – Advanced Triple PWM Only Mode and Dual Linear Power Controller for Portable Applications

ISL6235
Gate Control Logic
The gate control logic translates generated PWM control
signals into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operational conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control logic
provides adaptive dead time by monitoring the gate-to-
source voltages of both upper and lower MOSFETs. The
lower MOSFET is not turned on until the gate-to-source
voltage of the upper MOSFET has decreased to less than
approximately 1 volt. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1 volt.
This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
3.3V Main and 5V Main Soft Start, Sequencing and
Stand-by
See Table 1 for the output voltage control algorithm. The 5V
Main and 3.3V Main converters are enabled if SDWN1 and
SDWN2 are high and SDWNALL is also high. The stand-by
mode is defined as a condition when SDWN1 and SDWN2
are low and the PWM converters are disabled but
SDWNALL is high (3.3V ALWAYS and 5V ALWAYS outputs
are enabled). In this power saving mode, only the low power
micro-controller and keyboard may be powered.
TABLE 1. OUTPUT VOLTAGE CONTROL
3V AND 5V
SDWNALL SDWN1 SDWN2 ALWAYS 5V MAIN 3V MAIN
0
X
X
OFF
OFF
OFF
1
0
0
ON
OFF
OFF
1
1
0
ON
ON
OFF
1
0
1
ON
OFF
ON
1
1
1
ON
ON
ON
Soft start of the 3.3V Main and 5V Main converters is
accomplished by means of capacitors connected from pins
SDWN1 and SDWN2 to ground. In conjunction with 5µA
internal current sources, they provide a controlled rise of the
3.3V Main and 5V Main output voltages. The value of the
soft-start capacitors can be calculated from the following
expression.
Css = ⁵----^µ----^A------^×-----^T----^s---^s--
3.5 V
(EQ. 2)
Where T_ss is the desired soft-start time.
By varying the values of the soft-start capacitors, it is possible
to provide sequencing of the main outputs at start-up.
Figure 2 shows the soft-start initiated by the SDWNALL pin
being pulled high with the Vbatt input at 10.8V and the
resulting 3.3V Main and 5V Main outputs.
V_IN = 10.8V
SDWNALL,10V/DIV.
SDWN2, 2V/DIV.
0V
3.3V_OUT, 2V/DIV.
SDWN1, 2V/DIV.
0V
5V_OUT, 2V/DIV.
T0 T1 T2
T3 T4
4ms /DIV.
FIGURE 2. SOFT START ON 3.3V AND 5V OUTPUTS
While the SDWNALL pin is held low, prior to T0, all outputs
are off. Pulling SDWNALL high enables the 3.3V ALWAYS
and 5V ALWAYS outputs. With the 3.3V Main and 5V Main
outputs enabled, at T1, the internal 5mA current sources
start charging the soft start capacitors on the SDWN1 and
SDWN2 pins. At T2 the outputs begin to rise and because
they both have the same value of soft-start capacitors,
0.022mF, they both reach regulation at the same time, T3.
The soft-start capacitors continue to charge and are
completely charged at T4.
12V Converter Architecture
The 12V boost converter generates its output voltage from
the 5V Main output. An external MOSFET, inductor, diode
and capacitor are required to complete the circuit. The
output signal is fed back to the controller via an external
resistive divider. The boost controller can be disabled by
connecting the VSEN3 pin to 5V ALWAYS.
The control circuit for the 12V converter consists of a 3:1
frequency divider which drives a ramp generator and resets a
PWM latch as shown in Figure 3. The width of the CLK/3
pulses is equal to the period of the main clock, limiting the
duty cycle to 33%. The output of a non-inverting error
amplifier is compared with the rising ramp voltage. When the
ramp voltage becomes higher than the error signal, the PWM
comparator sets the latch and the output of the gate driver is
pulled high providing leading edge, voltage mode PWM. The
falling edge of the CLK/3 pulses resets the latch and pulls the
output of the gate driver low.
8