ISL6235 Datasheet, PDF (11/14 Pages) Intersil Corporation – Advanced Triple PWM Only Mode and Dual Linear Power Controller for Portable Applications

ISL6235
5
4.5
4
IN-PHASE
3.5
3
OUT-OF-PHASE
2.5
5V
2
1.5
3.3V
1
0.5
0
0
1
2
3
4
5
3.3V AND 5V LOAD CURRENT
INPUT CAPACITANCE RMS CURRENT AT VIN = 10.8V
FIGURE 4. INPUT RMS CURRENT VS LOAD
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
For board designs that allow through-hole components, the
Sanyo OS-CON_TM series offer low ESR and good
temperature performance.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be
capable of handling the surge-current at power-up. The TPS
series available from AVX is surge current tested.
+12V Boost Converter Inductor Selection
The inductor value is chosen to provide the required output
power to the load.
Lmax= ^V-----ⁱ--ⁿ----^m-----ⁱ--ⁿ---²-----^×-----^D-----^m-----^a----^x---²----^×-----^R-----^o--
2 × Vo² × F
(EQ. 9)
where, V_inmin is the minimum input voltage, 4.9V; D_max =
1/3, the maximum duty cycle; R_o is the minimum load
resistance; V_o is the nominal output voltage and F is the
switching frequency, 100kHz.
Or, for L in uH, the maximum output current is nominally:
Imax= --¹---³---^.--⁸---⁸---
L × Vo
(EQ. 10)
+12V Boost Converter Output Capacitor Selection
The total capacitance on the 12V output should be chosen
appropriately, so that the output voltage will be higher than
the undervoltage limit (9V) when the 5V Main soft-start time
has elapsed. This will avoid triggering of the 12V
undervoltage protection.
The maximum value of the boost capacitor, Comax that will
charge to 9V in the soft start time, T_SS, is shown below,
where L is the value of the boost inductor.
Comax
=
T_-----s_---s_-
L
×
0.115 µ F
(EQ. 11)
The output capacitor ESR and the boost inductor ripple
current determines the output voltage ripple. The ripple
voltage is given by:
V_RIPPLE = ∆IL × ESR
(EQ. 12)
and the maximum ripple current, ∆I_L, is given by:
∆IL
=
5_----V_---
L
× 3.3µ
(EQ. 13)
where L is the boost inductor calculated above, 5V is the
boost input voltage and 3.3µ is the maximum on time for the
boost MOSFET.
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon r_DS(ON) , gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
P_UPPER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----V_{----O-----U----T-- + -}I_-O------×_-----V_{----I--N-----}×_-----t_{--S----W------}×_-----F_----S--
V_IN
2
(EQ. 14)
P_LOWER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----(_---V_{----I--N-----–----}V_{-----O----U----T----})
V_IN
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the ISL6235 and do not heat the MOSFETs.
However, a large gate-charge increases the switching time,
t_SW which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
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