ISL6235 Datasheet, PDF (7/14 Pages) Intersil Corporation – Advanced Triple PWM Only Mode and Dual Linear Power Controller for Portable Applications

ISL6235
General Description
The ISL6235 addresses the system electronics power needs
of modern notebook and LCD PCs that require a fixed
frequency, PWM mode only, controller. The ISL6235 is
similar to the IPM6220A but without the Hysteretic mode of
operation. The IC integrates control circuits for two
synchronous buck converters for 5V Main and 3.3V Main
buses, two linear regulators for 3.3V ALWAYS and 5V
ALWAYS, and a flexible boost converter, nominally 12V.
The two synchronous converters operate out of phase to
substantially reduce the input-current ripple, minimizing input
filter requirements, minimizing battery heating and
prolonging battery life.
The 12V boost controller uses a 100kHz clock derived from
the main clock. This controller uses leading edge modulation
with the maximum duty cycle limited to 33%.
The chip has three input control lines SDWN1, SDWN2 and
SDWNALL. These are provided for Advanced Configuration
and Power Interface (ACPI) compatibility. They turn on and
off all outputs, as well as provide independent control of the
3.3V Main and +5V Main outputs.
To maximize efficiency for the 5V Main and 3.3V Main outputs,
the current-sense technique is based on the lower MOSFET
r_DS(ON).
3.3V Main and 5V Main Architecture
These main outputs are generated from the unregulated
battery input by two independent synchronous buck
converters. The IC integrates all the components required
for output voltage setpoint and feedback compensation,
significantly reducing the number of external components,
saving board space and parts cost.
The buck PWM controllers employ a 300kHz fixed frequency
current-mode control scheme with input voltage feed-
forward ramp programming for better rejection of input
voltage variations.
Figure 1 shows the out-of-phase operation for the 3.3V Main
and 5V Main outputs. The phase node is the junction of the
upper MOSFET, lower MOSFET and the output inductor.
The phase node is high when the upper MOSFET is
conducting and the inductor current rises accordingly. When
the phase node is low, the lower MOSFET is conducting and
the inductor current is ramping down as shown.
V_IN = 10.8V
5A
I_L3.3V (2A/DIV.)
3.3V PHASE (10V/DIV.)
0 A, V
5A
I_L5V (2A/DIV.)
0 A, V
5V PHASE (10V/DIV.)
1µs/DIV.
FIGURE 1. OUT OF PHASE OPERATION
Current Sensing and Current Limit Protection
Both PWM converters use the lower MOSFET on-state
resistance, r_DS(ON), as the current-sensing element. This
technique eliminates the need for a current sense resistor
and the associated power losses. If more accurate current
protection is desired, current sense resistors may be used in
series with the lower MOSFETs’ source.
To set the current limit, place a resistor, RSNS, between the
ISEN inputs and the drain of the lower MOSFET (or optional
current sense resistor). The required value of the RSNS
resistor is determined from the following equation:
RSNS
=
----^R-----^c---^s-----
135 µ A
 ^I
oc
dc
+
L^-----×^-----2^-----×^--V---3^--o-0^---0^----k^----H^-----z^{-}
– 100
(EQ. 1)
where Iocdc is the desired DC overcurrent limit; Rcs is either
the r_DS(ON) of the lower MOSFET, or the value of the optional
current-sense resistor, Vo is the output voltage and L is the
output inductor. Also, the value of Rcs should be specified
for the expected maximum operating temperature.
The sensed voltage, and the resulting current out of the
ISEN pin through RSNS, is used for current feedback and
current limit protection. This is compared with an internal
current limit threshold. When a sampled value of the output
current is determined to be above the current limit
threshold, the PWM drive is terminated and a counter is
initiated. This limits the inductor current build-up and
essentially switches the converter into current-limit mode. If
an overcurrent is detected between 26µs to 53µs later, an
overcurrent shutdown is initiated. If during the 26µs to 53µs
period, an overcurrent is not detected, the counter is reset
and sampling continues as normal.
This current limit scheme has proven to be very robust in
applications like portable computers where fast inductor
current build-up is common due to a large difference
between input and output voltages and a low value of the
inductor.
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