ISL6228_14 Datasheet, PDF (8/16 Pages) Intersil Corporation – High-Performance Dual-Output Buck Controller for Notebook Applications

ISL6228
current through C_R is provided by a transconductance
amplifier g_m that measures the VIN and VO pin voltages.
The positive slope of V_R can be written as Equation 1:
V_RPOS = (g_m) ⋅ (V_IN – V_OUT) ⁄ C_R
(EQ. 1)
The negative slope of V_R can be written as Equation 2:
V_RNEG = g_m ⋅ V_OUT ⁄ C_R
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is set by a resistor connected across the FSET and GND
pins. The V_R, V_COMP, and V_W signals feed into a window
comparator in which V_COMP is the lower threshold voltage
and V_W is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as V_R traverses the V_W and
V_COMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V_R; it is inversely proportional to the voltage
between V_W and V_COMP.
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
Soft-Start Delay t_SS begins and the output voltage begins to
rise. The FB pin ramps to 0.6V in approximately 1.5ms and
the PGOOD pin goes to high impedance approximately
1.25ms after the FB pin voltage reaches 0.6V.
1.5ms
Vo
VCC and PVCC
EN
FB
1.25ms
PGOOD
FIGURE 3. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if V_CC has not reached the rising POR
threshold V_CCR, or if V_CC is below the falling POR threshold
V_CCF. The ISL6228 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. The PGOOD
pull-down resistance is 95Ω during soft-start or if an UVP
occurs, 30Ω for an OCP, or 60Ω for OVP.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft-start or Undervoltage
90Ω
Overvoltage
60Ω
Overcurrent
30Ω
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Power-On Reset
The ISL6228 is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) V_CCR
threshold voltage. The controller will be disabled when the
voltage at the VCC pin decreases below the falling POR
V_CCF threshold voltage.
EN, Soft-Start and PGOOD
The ISL6228 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage V_ENTHR, the PGOOD
MOSFET Gate-Drive Outputs LGATE and UGATE
The ISL6228 has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The low-side gate-drivers
are optimized for low duty-cycle applications where the low-
side MOSFET conduction losses are dominant, requiring a
low r _DS(ON) MOSFET. The LGATE pull-down resistance is
small in order to clamp the gate of the MOSFET below the
V_GS(th) at turnoff. The current transient through the gate at
turn-off can be considerable because the gate charge of a
low r _DS(ON) MOSFET can be large. Adaptive shoot-through
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 4 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The typical dead-time is 21ns.
The high-side gate-driver output voltage is measured across
the UGATE and PHASE pins while the low-side gate-driver
output voltage is measured across the LGATE and PGND
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FN9095.2
May 7, 2008