ISL6228_14 Datasheet, PDF (10/16 Pages) Intersil Corporation – High-Performance Dual-Output Buck Controller for Notebook Applications

ISL6228
The ISL6228 monitors the OCSET pin and the VO pin
voltages. Once the OCSET pin voltage is higher than the VO
pin voltage for more than 10µs, the ISL6228 declares an OCP
fault. The value of R_OCSET is then written as Equation 6:
R_OCSET
=
-^I-^O-----^C-----^•--^D-----^C-----^R---
10 μ A
(EQ. 6)
Where:
- R_OCSET (Ω) is the resistor used to program the
overcurrent setpoint
- I_OC is the output current threshold that will activate the
OCP circuit
- DCR is the inductor DC resistance
For example, if I_OC is 20A and DCR is 4.5mΩ, the choice of
R_OCSET is R_OCSET = 20A x 4.5mΩ/10µA = 9kΩ.
Resistor R_OCSET and capacitor C_SEN form an R-C network
to sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R_OCSETC_SEN
needs to match the inductor time constant L/DCR. The value
of C_SEN is then written as Equation 7:
C_SEN
=
--------------------^L---------------------
R_OCSET • DCR
(EQ. 7)
For example, if L is 1.5µH, DCR is 4.5mΩ, and R_OCSET is
9kΩ, the choice of C_SEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
Upon converter startup, capacitor C_SEN initial voltage is 0V.
To prevent false OCP, a 10µA current source flows out of the
VO pin during start up, generating a voltage drop on resistor
R_O, which has the same resistance as R_OCSET. When
PGOOD pin goes high, the VO pin current source will
terminate.
When an OCP fault is declared, the PGOOD pin will pull
down to 30Ω and latch off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V_ENTHF or if V_CC has decayed below the
falling POR threshold voltage ^V_{VCC_THF}.
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin voltage
is above the rising overvoltage threshold V_OVR for more than
2µs. The FB pin voltage is 0.6V in normal operation. The rising
overvoltage threshold V_OVR is typically 116%. That means if
the FB pin voltage is above 116% x 0.6V = 0.696V, for more
than 2µs, an OVP fault is declared.
When an OVP fault is declared, the PGOOD pin will pull
down to 60Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V_ENTHF or if V_CC has decayed
below the falling POR threshold voltage ^V_{VCC_THF}.
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the ability
to toggle the low-side MOSFET on and off, in response to
the output voltage transversing the V_OVR and V_OVF
thresholds. The LGATE gate-driver will turn on the low-side
MOSFET to discharge the output voltage, protecting the
load. The LGATE gate-driver will turn off the low-side
MOSFET once the FB pin voltage is lower than the falling
overvoltage threshold V_OVF for more than 2µs. The falling
overvoltage threshold V_OVF is typically 106%. That means if
the FB pin voltage falls below 106% x 0.6V = 0.636V, for
more than 2µs, the LGATE gate-driver will turn off the low-
side MOSFET. If the output voltage rises again, the LGATE
driver will again turn on the low-side MOSFET when the FB
pin voltage is above the rising overvoltage threshold V_OVR
for more than 2µs. By doing so, the ISL6228 protects the
load when there is a consistent overvoltage condition.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V_UV for more
than 2µs. The FB pin voltage is 0.6V in normal operation.
The undervoltage threshold V_UV is typically 86%. That
means if the FB pin voltage is below 86% x 0.6V = 0.516V,
for more than 2µs, an UVP fault is declared, and the
PGOOD pin will pull down to 95Ω and latch-off the converter.
The fault will remain latched until the EN pin has been pulled
below the falling EN threshold voltage V_ENTHF or if V_CC has
decayed below the falling POR threshold voltage
V_{VCC_THF.}
Programming the Output Voltage
When the converter is in regulation there will be 0.6V from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 0.6V with respect to the GND
pin when the converter is regulating at the desired output
voltage. The output voltage can be programmed from 0.6V
to 5V.
Programming the output voltage is written as Equation 8:
V_REF
=
V
O
•
------------^R----^B----^O-----^T---^T----^O----^M--------------
R_TOP + R_BOTTOM
(EQ. 8)
Where:
- V_O is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the V_REF
- R_TOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- R_BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose R_TOP value first, and calculate R_BOTTOM according
to Equation 9:
R_BOTTOM
=
V_{-----R----E----F----}•_---R_{----T----O----P--}
V_O – V_REF
(EQ. 9)
10
FN9095.2
May 7, 2008